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? add/drop four 2.048 mbit/s signals from stm-1/vc-4, sts-3/au-3 or sts-1 buses independent add and drop bus timing modes selectable hdb3 positive/negative rail or nrz e1 interface. performance counter provided for cod- ing violations. digital desynchronizer drop buses are monitored for parity, loss of clock, upstream ais and h4 multiframe errors performance counters are provided for tu/vt pointer movements, bip-2 errors and far end block errors (febes) tu/vts are monitored for loss of pointer, new data flags (ndfs), ais, remote defect indication (rdi), and size errors (s-bits) v5 byte signal label mismatch and unequipped detection e1 facility and line loopbacks, generation of bip-2 and febe errors, and send rdi capability intel / motorola / multiplexed-compatible micropro- cessor bus interface with interrupt capability programmable internal risc processor imple- ments vt-poh and vt-alarm handling j2 16-byte etsi trail trace comparison optional v4 receive and transmit byte access tu tandem connection processing (n2 byte) ieee 1149.1 standard boundary scan single +5 v 5 % power supply 160-lead plastic quad flat package or 208-lead pbga (17 mm x 17 mm) the quad e1 mapper device is designed for add/drop multiplexer, terminal multiplexer, and dual and single uni- directional ring applications. four e1 2.048 mbit/s signals are mapped to and from asynchronous tributary unit-12 (tu-12) or virtual tributary 2 (vt2) formats. the qe1m interfaces to a multiple-segment, byte-parallel sdh/sonet-formatted bus at the 19.44 mbit/s byte rate for stm-1/sts-3 operation or at the 6.48 mbit/s byte rate for sts-1 operation. the e1 2.048 mbit/s signals can be either hdb3 positive/negative rail- or nrz-formatted sig- nals. the qe1m provides performance counters, alarm detection, and the ability to generate errors and alarm indication signals (ais). e1 facility and line loopback capabilities are also provided. the qe1m bus interface is used to connect to other transwitch devices such as the stm-1/sts-3/sts-3c overhead terminator (sot-3), txc-03003 or txc-03003b, to form an stm-1/sts-3 add/drop or ter- minal system. stm-1/sts-3/sts-1 to 2.048 mbit/s add/drop mux/demux unidirectional or bidirectional ring applications stm-1/sts-3/sts-1 termination terminal mode multiplexer stm-1/sts-3/sts-1 test equipment qe1m device quad e1 mapper txc-04252 document number: txc-04252-mb ed. 3, december 2000 data sheet u.s. patents no. 4,967,405; 5,033,064; 5,040,170; 5,265,096; 5,289,057; 5,297,180; 5,473,611; 5,528,598; 5,535,218; u.s. and/or foreign patents issued or pending copyright ? 2000 transwitch corporation transwitch and txc are registered trademarks of transwitch corporation +5v a - side drop bus external clock a - side add bus b - side drop bus b - side add bus por t 1 por t 2 por t 3 por t 4 7 7 7 7 microprocessor interface 13 14 13 14 stm-1/sts-3/sts-1 sdh/sonet side 2.048 mbit/s line side 3 controls 5 boundary scan qe1m quad e1 mapper tsc-04252 p & n data and clock for receive and transmit, plus receive data zero-output control proprietary transwitch corporation information for use solely by its customers. applications description features transwitch corporation ? 3 enterprise drive shelton, connecticut 06484 usa tel: 203-929-8810 fax: 203-926-9453 www.transwitch.com
qe1m txc-04252 - 2 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. table of contents section page list of figures................................................................................................................ ..................... 3 block diagram ................................................................................................................. .................. 4 block diagram description ..................................................................................................... ........... 5 lead diagrams ................................................................................................................. ................. 9 lead descriptions ............................................................................................................. ............... 11 absolute maximum ratings and environmental limitations ........................................................... 21 thermal characteristics ....................................................................................................... ............ 21 power requirements ............................................................................................................ ........... 21 input, output and input/output parameters .................................................................................... 2 2 timing characteristics ........................................................................................................ ............. 25 operation ..................................................................................................................... .................... 43 bus interface modes ........................................................................................................... ..... 43 bus mode selection ............................................................................................................ ..... 44 sdh/sonet add/drop multiplexing format selections .......................................................... 44 drop tu/vt selection .......................................................................................................... .... 45 add tu/vt selection ........................................................................................................... ..... 46 bus timing .................................................................................................................... ........... 47 unequipped operation .......................................................................................................... ... 47 drop bus multiframe alignment ................................................................................................ 4 9 add bus multiframe alignment ................................................................................................. 5 0 performance counters .......................................................................................................... ... 51 alarm structure ............................................................................................................... ......... 51 interrupt structure ........................................................................................................... ......... 52 sdh/sonet ais detection ..................................................................................................... 58 tu/vt pointer tracking ........................................................................................................ .... 59 remote defect indications ..................................................................................................... .. 61 overhead communications bit access .................................................................................... 64 bip-2, ais indication, tc rei and tc oei processing ............................................................ 68 tug-3 null pointer indicator .................................................................................................. .. 70 e1 loopback capability ........................................................................................................ ... 71 prbs pattern generator and analyzer .................................................................................... 72 resets ........................................................................................................................ .............. 72 start-up procedure ............................................................................................................ ...... 73 pointer leak rate calculations ................................................................................................ 74 jitter measurements ........................................................................................................... ...... 75 internal spot processor ....................................................................................................... ..... 80 boundary scan ................................................................................................................. ........ 84 multiplex format and mapping information .............................................................................. 93 memory map .................................................................................................................... ............... 99 memory map descriptions ....................................................................................................... ...... 105 package information ........................................................................................................... .......... 138 ordering information .......................................................................................................... ........... 140
qe1m txc-04252 - 3 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. related products .............................................................................................................. ............. 140 standards documentation sources .............................................................................................. 1 41 list of data sheet changes .................................................................................................... ...... 143 documentation update registration form * .............................................................................. 147 * please note that transwitch provides documentation for all of its products. customers who are using a transwitch product, or planning to do so, should register with the transwitch marketing department to receive relevant updated and supplemental documentation as it is issued. they should also contact the applications engineering department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product. list of figures figure page 1. qe1m txc-04252 block diagram......................................................................................... 4 2. 2048 kbit/s asynchronous mapping....................................................................................... 8 3. qe1m txc-04252 plastic quad flat package lead diagram .............................................. 9 4. qe1m txc-04252 plastic ball grid array package lead diagram..................................... 10 5. ports 1, 2, 3 and 4 e1 transmit timing ............................................................................... 25 6. ports 1, 2, 3 and 4 e1 receive timing ................................................................................ 26 7. sts-1 a/b drop and add bus signals, timing derived from drop bus .............................. 27 8. stm-1/sts-3 a/b drop and add bus signals, timing derived from drop bus .................. 28 9. sts-1 a/b add bus signals, timing derived from add bus ............................................... 29 10. stm-1/sts-3 a/b add bus signals, timing derived from add bus.................................... 30 11. microprocessor read cycle timing - multiplex bus ............................................................ 31 12. microprocessor write cycle timing - multiplex bus ............................................................ 33 13. microprocessor read cycle timing - intel........................................................................... 35 14. microprocessor write cycle timing - intel ........................................................................... 37 15. microprocessor read cycle timing - motorola.................................................................... 38 16. microprocessor write cycle timing - motorola ................................................................... 40 17. boundary scan timing ........................................................................................................ 42 18. h4 byte floating vt mode bit allocation............................................................................. 49 19. tu/vt pointer tracking state machine ............................................................................... 60 20. facility and line loopbacks ................................................................................................ 71 21. jitter tolerance and jitter test arrangements..................................................................... 76 22. jitter tolerance measurements ........................................................................................... 76 23. jitter transfer measurements.............................................................................................. 7 7 24. standard pointer test sequences....................................................................................... 79 25. schematic diagram of qe1m showing spot processor interfaces................................... 82 26. recommended implementation flowchart for reprogramming the spot processor ........ 83 27. boundary scan schematic .................................................................................................. 85 28. qe1m txc-04252 160-lead plastic quad flat package.................................................. 138 29. qe1m txc-04252 208-lead plastic ball grid array package .......................................... 139
qe1m txc-04252 - 4 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. block diagram figure 1. qe1m txc-04252 block diagram tu/vt te r m i n a t e a side tu/vt terminate b side destuff b receive (b drop) a transmit (a add) tu/vt build b side tu/vt build a side stuff/sync a side stuff/sync b side hdb3 decoder hdb3 coder desync p i/o repeated for ports 1, 2, 3 and 4 alarms & controls repeated for ports 1, 2, 3 and 4 alarms controls, & timing test abust highz reset extck quietn rpon rnon rcon motorola mode select: moto add., add.: upa(10-8), a(10-8) add. & data, add.: upad(7-0), a(7-0) nu*, data: nu*, d(7-0) select, select: sel , sel read, read / read/write: rd ,rd /rd/wr write, write/select: wr ,wr /lds tpin tnin/tlos n tcin a drop a add b drop b add b transmit (b add) 13 14 13 14 te s t port access tck tms tdi tdo trs ieee 1149.1 boundary scan input/output a receive (a drop) ready, ready/dt ack: rdy, rdy/dtack mux mode select: mux mux, intel/motorola functions: symbols interrupt, interrupt: int, int/irq interrupt sense select: intsh, intsh add. latch enable, nu*: ale, nu* 3 8 8 * note: nu=lead not used in this mode spot risc and ram 12 1 12 1 3 11 3 11 sdh/sonet side line side line side processor ? ? ? ? ? ? ?
qe1m txc-04252 - 5 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. block diagram description the block diagram for the quad e1 mapper is shown in 1. the quad e1 mapper interfaces to four buses, des- ignated as a drop, b drop, a add, and b add. the four buses run at the stm-1/sts-3 rate of 19.44 mbyte/s, or at the sts-1 rate of 6.48 mbyte/s. for north american applications, the asynchronous e1 signals are car- ried in floating virtual tributary 2 (vt2) format in a synchronous transport signal - 1 (sts-1), or in an sts-1 that is carried in a synchronous transport signal - 3 (sts-3). for itu-t applications, the e1 signals are car- ried in floating mode tributary unit - 12 (tu-12) format in the stm-1 virtual container - 4 structure (vc-4) using tributary unit group - 3 (tug-3), or in the stm-1 virtual container - 3 structure (vc-3) using tributary unit group -2 (tug-2) mapping schemes. four e1 signals can be dropped from one bus (a drop or b drop), or from both of the drop buses, to the e1 lines. four asynchronous e1 signals are converted into tu-12 or vt2 format and are added to either of the add buses, or both, depending upon the mode of operation. when the quad e1 mapper is configured for dro p bus timing, the add buses are, by definition, byte- and multiframe-syn- chronous with their like-named drop buses, but are delayed by one byte time because of internal processing. for example, if a byte in the stm-1 virtual container - 4 structure (vc-4) using tributary unit group - 3 (tug-3), tu-12/vt2 is to be added to the a add bus, the time of its placement on the bus is derived from the a drop bus timing, and from software instructions specifying which tu/vt number is being dropped/added. when the device is configured for add bus timing, the add bus, parity, and add indicator signals are derived from the add clock, c1j1v1 and spe signals. the a receive block is identical to the b receive block. the tu/vt terminate block is repeated 8 times, two for each port (a and b sides). the destuff, desync, and hdb3 coder blocks are repeated four times, one for each port. the interface between a drop bus and receive block consists of 12 input leads, and an optional out- put lead: a byte clock, byte-wide data, a c1j1 indicator which may be carrying a v1 indication making the sig- nal a c1j1v1 indicator, an spe indicator, and an odd parity bit for the last-named three signals. parity is selectable by control bits for even parity and for the data byte only. the output lead is an optional tu/vt select indicator signal. the drop c1j1v1 signal is used in conjunction with the drop spe signal to determine the location of the various pulses. the c1 pulse identifies the location of the c1 byte when the spe signal is low. a single j1 pulse identifies the starting location of the j1 byte in the vc-4 format, when the spe signal is high. three j1 pulses are provided for the sts-3 format, each identifying the starting location of the j1 byte in each of the sts-1 signals. the quad e1 mapper can operate with a v1 pulse in the c1j1v1 signal, or it can use an internal h4 detector for determining the location of the v1 pulse. the v1 pulse location is used to determine the location of the pointer byte v1. for stm-1 vc-4 operation, if the c1j1v1 signal is used, a single v1 pulse must occur three drop bus clock cycles every four frames following the j1 pulse when the spe signal is high. for sts-3 opera- tion, three v1 pulses must be present every four frames. each of the three v1 pulses must be present three clock cycles after the corresponding j1 pulse, when the spe signal is high. for example, in a vc-4 signal, the j1 pulse identifies the j1 byte location (defined as the starting location for the vc-4) in the poh bytes. in the next column (first clock cycle) all the rows are assigned as fixed stuff. similarly, in the next column (second clock cycle) all the rows are assigned as fixed stuff. the next column (third clock cycle) defines the start of tug-3 a. this column is where the v1 pulse occurs every four frames. however, the actual v1 byte location is six clock cycles after the v1 pulse. for sts-1 operation, one v1 pulse must be present if the c1j1v1 signal is used. the v1 pulse must occur on the next clock cycle after the j1 pulse, and when the spe signal is high. the j1 pulse identifies the j1 byte location (defined as the starting location for the sts-1) in the poh bytes. in the next column (first clock cycle) the tus start. thus, the v1 pulse identifies the starting location of the first v1 byte in the signal. the rest of the v1 bytes for the 21 tu-12/vt2s are also aligned with respect to the v1 pulse (please see the first diagram in the operation - multiplex format and mapping information section). each bus is monitored for parity errors, loss of clock, h4 multiframe alignment if selected, and an upstream sdh/sonet ais indication. the quad e1 mapper can monitor either the toh e1 bytes or the h1/h2 bytes for an ais indication. which e1 byte and h1/h2 bytes are selected is a function of the tu/vt selected.
qe1m txc-04252 - 6 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. each tu/vt terminate block (a and b side) performs pointer processing based on the location of the v1 and v2 bytes. the pointer bytes are monitored for loss of pointer, tu ais indication, and ndf. the pointer tracking process is based on the latest etsi standard, which also meets ansi/bellcore requirements. pointer incre- ments and decrements are also counted, and the ss-bits are monitored for the correct value. this block also monitors the various alarms found in the v5 and k4 (formerly known as z7) bytes, including signal label mis- match detection, unequipped status detection, bip-2 parity error detection and error counter, febe counter, and the three rdi indications. the quad e1 mapper performs a 16-byte j2 trail trace comparison on the chan- nels selected. for 64-byte messages, the bytes are stored in a memory map segment for a microprocessor read cycle. the device also provides the tu tandem connection feature and performs the 16-byte message comparison for the n2 (formerly known as z6) byte message. a control bit for each port selects the tu/vt from either the a drop or b drop bus. the tu/vt is destuffed in the destuff block using majority logic rules for the three sets of three justification control bits to determine if the two s-bits are data bits or frequency justification bits. the desync block removes the effects on the e1 output of systemic jitter that might occur because of signal mappings and pointer movements in the network. the desync block contains two parts, a pointer leak buffer, and a e1 loop buffer. the pointer leak buffer can accept up to five consecutive pointer movements, and can adjust the effect over time. the e1 loop buffer consists of a digital loop filter, which is designed to track the fre- quency of the received e1 signal and to remove both transmission and stuffing jitter. an option for each port provides either nrz data, or an hdb3-encoded positive and negative rail signal for the e1 interface. receive data (towards the e1 line), for all four channels, can be clocked out on either rising or falling edges of the clock. in addition, control bits are provided for forcing the data and clock signals to a high impedance state (tristate). a control lead is provided for forcing the output leads to the 0 state. in the add direction, the quad e1 mapper accepts clock and either nrz data or hdb3-encoded positive and negative rail signals. data, for all four channels, can be clocked in on either the falling or rising edge of the clock. in the nrz mode, an external loss of clock indication input signal can be provided. for the rail signal, coding violations are counted, and there is monitoring for loss of signal. an e1ais detector is also provided. the data signal is written into a fifo in one of the eight stuff/sync blocks. threshold modulation is used for the frequency justification process. timing information from the drop bus or add bus is used to read the fifo and perform the tu/vt justification process. this block permits tracking of an incoming e1 signal having an average frequency offset as high as 120 ppm, and up to 1.5 ui of peak-to-peak jitter. since the quad e1 map- per supports a ring architecture, two sets of blocks are provided for each port. the tu/vt selection is the same for both blocks. a control bit, and transmit line alarms, can generate an e1ais. the eight tu/vt build blocks format the tu/vt into a sts-1, sts-3 or stm-1 structure for the asynchronous 2048 kbit/s signals, as shown in 2. the pointer value carried in the v1 and v2 bytes is transmitted with a fixed value of 105. transmit access is provided for the 8 overhead communications channel bits (o-bits) via the microprocessor. the microprocessor also writes the signal label, and the value of the j2 message, either as a 16-byte or a 64-byte message. the quad e1 mapper provides the tu tandem connection feature for the tu, including the transmission of the 16-byte message and the various alarms associated with the tandem connec- tion feature. the device provides three-bit rdi using the v5 and k4 (z7) bytes. local alarms, or the micropro- cessor, can generate the remote payload, server, or connectivity defect indications. the far end block error (febe) is inserted from the bip-2 errors detected on the receive side, and bip-2 parity is generated for the v5 byte. control bits are provided for generating unequipped status, generating tu/vt ais, and inserting febe and bip-2 errors. the ability to generate null pointer indicators (npis) is also provided for the stm-1 vc-4 for- mat. the a transmit block is identical to the b transmit block. the interface between an add bus and a transmit block consists of three input leads and eleven output leads, when the add bus timing mode is selected. the input leads are a byte clock, a c1j1v1 indicator, and an spe indicator. the output leads are byte-wide data, a parity indicator, an add indicator, and an optional tu/vt selection indicator signal. the add c1j1v1 signal is used in conjunction with the add spe signal to determine the location of the various pulses. an option is pro-
qe1m txc-04252 - 7 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. vided in which the drop side v1 reference pulse, either from the drop bus c1j1v1 indicator or from the h4 mul- tiframe detector, may be used as the add side v1 reference pulse. when drop bus timing is selected, the output leads are byte-wide data, a parity indicator, an add indicator, and an optional tu/vt selection indicator signal. the add bus clock, spe and c1j1v1 signals are disabled. the microprocessor input/output interface block consists of an intel-, motorola- or multiplexed address/data-compatible bus interface that provides access to assigned qe1m memory map addresses in the range from 000h to 7ffh (please see the memory map and memory map description sections for further infor- mation). interrupt capability is also provided. the alarms that cause the interrupt can be set on positive, nega- tive, or both positive and negative transitions, or on positive levels. interrupt mask bits are provided for register byte locations, and some defined bits. control bits are provided which enable an e1 facility or line loopback. because of the complexity of the sdh/sonet interface and the two timing modes, sdh/sonet loopback of the tu/vts is not supported. the spot (s onet p rocessor for o verhead t ermination) block is a risc processor with associated instruc- tion and data memory that performs selected low-speed functions, including all overhead processing and counter maintenance. the spot program must be loaded into the spot instruction memory after power-up. executable microcode is provided by transwitch (see the operations - internal spot processor section). the boundary scan interface block provides a five-lead test access port (tap) that conforms to the ieee 1149.1 standard. this standard provides external boundary scan functions to read and write the external input/output leads from the tap for board and component test.
qe1m txc-04252 - 8 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 2. 2048 kbit/s asynchronous mapping v5 r r r r r r r r 32 bytes (2048 kbit/s data) j2 c 1 c 2 o o o o r r c 1 c 2 r r r r r s 1 32 bytes (2048 kbit/s data) n2 (z6) 32 bytes (2048 kbit/s data) k4 (z7) c 1 c 2 o o o o r r tu-12/vt2 v1 (pointer byte) 35 bytes v4 (reserved) v2 (pointer byte) v3 (action) 35 bytes 35 bytes 35 bytes 500 s 140 bytes i = information o = overhead communications c n = justification control s n = justification opportunity r = fixed stuff (set to 0) (febe) rfi l 1 l 2 l 3 rdi bit 1 8 1 path overhead (v5) byte signal label ndf s 1 s 2 ididididid v 1 v 2 new data flag normal = 0110, 1110, 0010, 0100 or 0111 new = 1001, 0001, 1101, 1011 or 1000 positive justification = invert five i-bits negative justification = invert five d-bits pointer range = 0 - 139 decimal size s 1 s 2 = 10 bip-2 bip-2 = bit interleaved parity (2 bits) rei = remote error indication (formerly febe, far end block error indication) rfi = remote failure indication l 1 l 2 l 3 = signal label rdi = remote defect indication (formerly ferf, far end receive failure indication) r r r r r r r r 31 bytes (2048 kbit/s data) s 2 i i i i i i i r r r r r r r r vc-12 144 bytes r r r r r r r r r r r r r r r r rei (ferf)
qe1m txc-04252 - 9 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. lead diagrams figure 3. qe1m txc-04252 plastic quad flat package lead diagram nc vdd badd bapar ba7 ba6 gnd ba4 ba3 vdd ba2 ba1 ba0 gnd aa0 aa1 aa2 gnd aa4 aa5 aa6 vdd aa7 aapar aadd gnd ad0 ad1 ad2 vdd ad3 ad4 ad5 gnd ad7 adpar vdd test rdy (rdy/dtack ) gnd vdd upad6 (d6) upad7 (d7) gnd a0 highz gnd a1 vdd a3 a4 test rd (rd / rd/wr ) wr (wr /lds ) ale (not used) upa8 (a8) upa9 (a9) ad6 vdd upad0 (d0) a7 upad1 (d1) abust upad2 (d2) upad5 (d5) upad4 (d4) upad3 (d3) extck vdd a2 sel intsh a6 gnd reset int (int/irq ) vdd a5 ba5 aa3 upa10 (a10) moto mux gnd quiet3 tci3 tni3/tlos3 tpi3 vdd rco3 rno3 rpo3 vdd rco1 rno1 rpo1 gnd quiet1 tci1 tni1/tlos1 tpi1 aaind adind gnd adclk aaclk gnd aac1j1v1 aaspe adc1j1v1 adspe vdd trs tms tdo tdi tck gnd gnd quiet4 vdd rco4 rno4 rco2 rno2 rpo2 gnd quiet2 tci2 tni2/tlos2 tpi2 baind bdind gnd bdclk baclk bac1j1v1 baspe bdc1j1v1 bdspe vdd bdpar bd7 bd6 bd5 bd4 vdd bd3 bd2 bd1 bd0 gnd gnd gnd vdd rpo4 tpi4 tni4/tlos4 tci4 vdd 75 70 65 60 55 50 45 80 125 130 135 140 145 150 155 1 5 10 15 20 25 30 35 40 120 115 110 105 100 95 90 85 qe1m lead diagram (top view) txc-04252 note: see figure 28 for package information. x(y/z) format is used for microprocessor interface signals to identify multiplex (intel/motorola) interface functions, where these are different.
qe1m txc-04252 - 10 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 4. qe1m txc-04252 plastic ball grid array package lead diagram 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 trp mlkjhgfedcb note: this is the bottom view. the leads are solder balls. see figure 29 for package information. some signal symbols have been abbreviated to fit the space available. the symbols are shown in full in the lead descriptions section. 16 a n nc gnd gnd nc nc gnd gnd nc gnd gnd gnd gnd gnd gnd gnd gnd nc upa8 a7 gnd ale nc highz nc upad4 vdd rdy/dtack tci4 moto mux tni3 rco3 rco1 tci1 tpi1 nc gnd aaspe nc trs tdo tdi nc upa9 gnd quiet3 vdd vdd quiet1 nc aaclk adc1j1v1 vdd tms nc tck vdd nc upa10 tci3 rno3 rn01 nc nc aaind adclk nc adspe nc nc nc adpar nc nc tpi3 rpo3 rpo1 tni1 vdd nc gnd aac1j1v1 nc gnd ad6 ad7 nc a6 reset nc ad3 ad4 nc ad5 intsh ad0 ad1 vdd ad2 a4 a3 nc aa7 aadd aapar aa5 aa6 vdd nc a1 a2 vdd aa4 nc gnd a0 aa2 aa1 nc ba0 ba1 nc ba2 upad6 upad7 upad3 upad5 nc vdd ba3 ba5 ba4 upad1 gnd rco2 nc tni2 nc nc vdd bd5 gnd ba6 ba7 nc test rco4 rpo4 rpo2 tci2 vdd baspe bdpar nc bd0 bapar quiet4 tni4 rno4 nc nc tpi2 gnd nc bdspe bd6 vdd bd2 nc nc nc tpi4 nc rno2 quiet2 nc nc baclk bdc1j1v1 bd7 bd4 bd3 bd1 vdd vdd nc badd bdclk bdind bac1j1v1 baind upad0 upad2 aa0 aa3 rd wr sel test int/irq a5 vdd nc extck vdd vdd abust adind
qe1m txc-04252 - 11 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. lead descriptions power supply, ground and no connect note: i = input; o = output; p = power; t=tristate symbol 160-lead pqfp lead no. 208-lead pbga lead no. i/o/p * type name/function vdd 9, 13, 22, 34, 41, 49, 57, 70, 79, 86, 92, 103, 115, 123, 131, 137, 142, 154 a14, b6, b11, c10, d9, d16, e2, f2, h4, h14, m2, m13, n12, n15, r6, r8, t2, t16 p vdd: +5 volt supply voltage, 5%. gnd 4, 17, 25, 27, 29, 40, 45, 53, 61, 66, 74, 81, 97, 100, 108, 120, 127, 134, 139, 151 a9, c2, d13, g7, g8, g9, g10, h8, h9, j7, j8, j9, j10, j15, k1, k4, k8, k9, n4, p13, t9 p ground: 0 volt reference. nc 80 a1, a5, a6, a11, b3, b4, b14, b16, c4, d5, d12, d15, e16, f13, f15, g3, g15, h2, h3, h7, h10, h13, h16, j1, j4, j16, k7, k10, k13, k15, l3, m1, m4, n3, n7, n14, p2, p3, p9, r3, r5, r10, r11, r15, t1, t4, t8, t15 no connect: nc leads are not to be connected, not even to another nc lead, but must be left floating. con- nection of these leads may impair performance or cause damage to the device.
qe1m txc-04252 - 12 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. a drop and a add bus i/o symbol 160-lead pqfp lead no. 208-lead pbga lead no. i/o/p type * name/function adclk 26 k3 i ttl a drop bus clock: this clock operates at 19.44 mhz for stm-1/sts-3 operation, and at 6.48 mhz for sts-1 opera- tion. a drop bus byte-wide data (ad7-ad0), the parity bit (adpar), spe indication (adspe), and the c1j1v1 indica- tion (adc1j1v1) are clocked in on falling edges of this clock. this clock may also be used for timing and deriving the like-named add bus byte-wide data, add and tu/vt indi- cations, and parity bits. the add bus signals are clocked out on rising edges of the clock during the time slots that corre- spond to the selected tu/vt. adpar 42 t3 i ttl a drop bus parity bit: an odd parity bit input signal repre- senting the parity calculation for each data byte, spe, and c1j1v1 signal from the drop bus. control bits are provided in address 012h which enable parity to be calculated as even (control bit dpe is 1), and/or for the data byte only (control bit pddo is 1). ad(7-0) 43, 44, 46-48, 50-52 r4, p4, t5, p5, n5, t6, p6, n6 i ttl a drop bus data byte: byte-wide data that corresponds to the stm-1/sts-3/sts-1 signal from the drop bus. the first bit received (dropped) corresponds to bit 7. adspe 33 m3 i ttl a drop bus spe indicator: a signal that is active high dur- ing each byte of the stm-1/sts-3/sts-1 payload, and low during transport overhead times. adc1j1v1 32 l2 i ttl a drop bus c1j1v1 indications: an active high timing sig- nal that carries stm-1/sts-3/sts-1 starting frame and spe information. this signal works in conjunction with the adspe signal. the c1 pulse identifies the location of the first c1 byte in the stm-1/sts-3 signal, and the c1 byte in the sts-1 signal, when adspe is low. the j1 signal identi- fies the starting location of the j1 signal when adspe is high. one or more v1 pulses may be present depending upon the format. the v1 pulses may be used in place of the h4 byte as the multiframe indication. adind 24 j2 o cmos 4ma a drop bus tu/vt selection indication: enabled when control bit adnen is written with a 1. an active low signal that is clocked out for the time slots determined by tu/vt selection (rtunn register) for each port (n=port number, 1-4). *see input, output and input/output parameters section below for type definitions.
qe1m txc-04252 - 13 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. aaclk 28 k2 i ttl a add bus clock: when the add bus timing mode is selected, this input must be provided for add bus timing. this clock operates at 19.44 mhz for stm-1/sts-3 operation, and at 6.48 mhz for sts-1 operation. the add bus spe indi- cation (aaspe), and the c1j1v1 indication (aac1j1v1) are clocked in on falling edges of this clock. add bus byte-wide data (aa7-aa0), add indicator (aadd ), and parity bit (aapar) are clocked out on rising edges of the clock during the time slots that correspond to the selected tu/vt. when drop bus timing is selected, this input is disabled. aapar 55 t7 o(t) cmos 4ma a add bus parity bit: an odd parity output signal that is calculated over the byte-wide add data. this tristate lead is only active when there is data being added to the add bus. when control bit ape is 1, even parity is calculated. aa(7-0) 56, 58, 59, 60, 62, 63, 64, 65 p7, p8, n8, n9, r9, n10, p10, t10 o(t) cmos 4ma a add bus data byte: byte-wide data that corresponds to the selected tu/vt. aaspe 31 l1 i ttl a add bus spe indicator: when the add bus timing mode is selected, this signal must be provided for add bus timing. this signal must be high during each byte of the stm-1/sts-3/sts-1 payload, and low during transport overhead byte times. aac1j1v1 30 l4 i ttl a add bus c1j1v1 indications: when the add bus timing mode is selected, this signal must be provided for add bus timing. an active high timing signal that carries stm-1/sts-3/sts-1 starting frame and spe information. this signal works in conjunction with the aaspe signal. the c1 pulse identifies the location of the first c1 byte in the stm-1/sts-3 signal, and the c1 byte in the sts-1 signal, when aaspe is low. the j1 signal identifies the starting location of the j1 signal when aaspe is high. the j1 signal identifies the location of the j1 byte. one or more v1 pulses may be present depending upon the format. the v1 pulses are used in place of the h4 byte as the multiframe indication. aaind 23 j3 o cmos 4ma a add bus tu/vt selection indication: enabled when control bit aanen is written with a 1. an active low signal that is clocked out for the time slots determined by tu/vt selection (ttunn register) for each port (n=port number, 1-4). aadd 54 r7 o cmos 4ma a add bus add data present indicator: this normally active low signal is present when output data to the a add bus is valid. it identifies the location of all of the tu/vt time slots being selected. when control bit addi is 1, the indica- tor is active high instead of active low. symbol 160-lead pqfp lead no. 208-lead pbga lead no. i/o/p type * name/function
qe1m txc-04252 - 14 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. b drop and b add bus i/o symbol 160-lead pqfp lead no. 208-lead pbga lead no. i/o/p type name/function bdclk 99 k14 i ttl b drop bus clock: this clock operates at 19.44 mhz for stm-1/sts-3 operation, and at 6.48 mhz for sts-1 opera- tion. b drop bus byte-wide data (bd7-bd0), the parity bit (bdpar), spe indication (bdspe), and the c1j1v1 indica- tion (bdc1j1v1) are clocked in on falling edges of this clock. this clock may also be used for timing and deriving the like-named add bus byte-wide data, add and tu/vt indi- cations, and parity bits. the add bus signals are clocked out on rising edges of the clock during the time slots that corre- spond to the selected tu/vt. bdpar 91 m14 i ttl b drop bus parity bit: an odd parity bit input signal repre- senting the parity calculation for each data byte, spe, and c1j1v1 signal from the drop bus. control bits are provided in address 012h which enable parity to be calculated as even (control bit dpe is 1), and/or for the data byte only (control bit pddo is 1). bd(7-0) 90-87, 85-82 m16, m15, n13, n16, p16, p15, r16, p14 i ttl b drop bus data byte: byte-wide data that corresponds to the stm-1/sts-3/sts-1 signal from the drop bus. the first bit received (dropped) corresponds to bit 7. bdspe 93 l15 i ttl b drop bus spe indicator: a signal that is active high dur- ing each byte of the stm-1/sts-3/sts-1 payload, and low during transport overhead times. bdc1j1v1 94 l16 i ttl b drop bus c1j1v1 indications: an active high timing sig- nal that carries stm-1/sts-3/sts-1 starting frame and spe information. this signal works in conjunction with the bdspe signal. the c1 pulse identifies the location of the first c1 byte in the stm-1/sts-3 signal, and the c1 byte in the sts-1 signal, when bdspe is low. the j1 signal identi- fies the starting location of the j1 signal when bdspe is high. one or more v1 pulses may be present depending upon the format. the v1 pulses may be used in place of the h4 byte as the multiframe indication. bdind 101 j14 o cmos 4ma b drop bus tu/vt selection indication: enabled when control bit bdnen is written with a 1. an active low signal that is clocked out for the time slots determined by tu/vt selection (rtunn register) for each port (n=port number, 1-4).
qe1m txc-04252 - 15 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. baclk 98 k16 i ttl b add bus clock: when the add bus timing mode is selected, this input must be provided for add bus timing. this clock operates at 19.44 mhz for stm-1/sts-3 operation, and at 6.48 mhz for sts-1 operation. the add bus spe indi- cation (baspe), and the c1j1v1 indication (bac1j1v1) are clocked in on falling edges of this clock. add bus byte-wide data (ba7-ba0), add indicator (badd ), and parity bit (bapar) are clocked out on rising edges of the clock during the time slots that correspond to the selected tu/vt. when drop bus timing is selected, this input is disabled. bapar 77 t14 o(t) cmos 4ma b add bus parity bit: an odd parity output signal that is calculated over the byte-wide add data. this tristate lead is only active when there is data being added to the add bus. when control bit ape is 1, even parity is calculated. ba(7-0) 76, 75, 73, 72, 71, 69, 68, 67 t13, r13, r12, t12, p12, t11, p11, n11 o(t) cmos 4ma b add bus data byte: byte-wide data that corresponds to the selected tu/vt. baspe 95 l14 i ttl b add bus spe indicator: when the add bus timing mode is selected, this signal must be provided for add bus timing. this signal must be high during each byte of the stm-1/sts-3/sts-1 payload, and low during transport overhead byte times. bac1j1v1 96 l13 i ttl b add bus c1j1v1 indications: when the add bus timing mode is selected, this signal must be provided for add bus timing. an active high timing signal that carries stm-1/sts-3/sts-1 starting frame and spe information. this signal works in conjunction with the baspe signal. the c1 pulse identifies the location of the first c1 byte in the stm-1/sts-3 signal, and the c1 byte in the sts-1 signal, when baspe is low. the j1 signal identifies the starting location of the j1 signal when baspe is high. the j1 signal identifies the location of the j1 byte. one or more v1 pulses may be present depending upon the format. the v1 pulses are used in place of the h4 byte as the multiframe indication. baind 102 j13 o cmos 4ma b add bus tu/vt selection indication: enabled when control bit banen is written with a 1. an active low signal that is clocked out for the time slots determined by tu/vt selection (ttunn register) for each port (n=port number, 1-4). badd 78 r14 o cmos 4ma b add bus add data present indicator: this normally active low signal is present when output data to the b add bus is valid. it identifies the location of all of the tu/vt time slots being selected. when control bit addi is 1, the indica- tor is active high instead of active low. symbol 160-lead pqfp lead no. 208-lead pbga lead no. i/o/p type name/function
qe1m txc-04252 - 16 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. port n line interface (n = 1, 2, 3 or 4) microprocessor bus interface selection symbol 160-lead pqfp lead no. 208-lead pbga lead no. i/o/p type name/function rcon (n=1-4) 14, 111, 10, 114 f1, e13, e1, d14 o(t) cmos 4ma receive port n output clock: a 2.048 mhz clock out- put. data is normally clocked out on rising edges of this clock. when control bit rcki is 1, data is clocked out on falling edges of this clock. when control bit rnen is 0, this lead is forced to a high impedance state. rpon (n=1-4) 16, 109, 12, 112 f4, f14, e4, e14 o(t) cmos 4ma receive port n data positive rail or nrz: when con- trol bit bypasn is 0, positive rail data is provided on this lead. when control bit bypasn is 1, an nrz signal is provided on this lead. when control bit rnen is 0, this lead is forced to a high impedance state. rnon (n=1-4) 15, 110, 11, 113 f3, f16, e3, e15 o(t) cmos 4ma receive port n data negative rail: when control bit bypasn is 0, negative rail data is provided on this lead. when control bit rnen is 0, or control bit bypasn is 1, this lead is forced to a high impedance state. tcin (n=1-4) 19, 106, 6, 118 g1, g14, d3, a16 ittl transmit port n input clock: a 2.048 mhz clock input. data is normally clocked in on falling edges of this clock. when control bit tcki is 1, data is clocked in on the ris- ing edges of this clock. tpin (n=1-4) 21, 104, 8, 116 h1, h15, d4, c16 ittl transmit port n data positive rail or nrz: when con- trol bit bypasn is 0, positive rail input data is provided on this lead. when control bit bypasn is 1, an nrz sig- nal is provided on this lead. tnin/ tlosn (n=1-4) 20, 105, 7, 117 g4, g13, d1, c15 ittl transmit port n data negative rail/external loss of signal: when control bit bypasn is 0, negative rail input data is provided on this lead. when control bit bypasn is 1, this lead may be used to input an active low exter- nal loss of signal indicator from the line interface device. quietn (n=1-4) 18, 107, 5, 119 g2, g16, d2, b15 ittl quiet port n: a high forces the rpon and rnon leads to the 0 state for either a rail or nrz interface, overriding control bit rnen when it is 0. a low disables this feature. symbol 160-lead pqfp lead no. 208-lead pbga lead no. i/o/p type name/function mux 3 c1 i ttl multiplex mode: a high placed on this lead configures the microprocessor bus to a multiplexed address/data bus inter- face. a low configures the intel or motorola interfaces (see symbol moto below).
qe1m txc-04252 - 17 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. microprocessor bus interface - multiplexed bus moto 2 b1 i ttl motorola mode : enabled when a low is placed on the mux lead. the following table lists the bus selection options. mux moto action h l or h multiplex bus interface l l intel bus interface l h motorola bus interface this selection modifies some bus interface lead functions, as described in the next two sections of this table. symbol 160-lead pqfp lead no. 208-lead pbga lead no. i/o/p type name/function upa(10-8) 1, 160, 159 c3, b2, a2 i (note 1) ttl (note 1) address bus: these are additional address lines for accessing qe1m memory locations (most signif- icant three bits). upa10 is the most significant bit. high is logic 1. upad(7-0) 133, 132, 130, 129, 128, 126, 125, 124 d11, c11, c12, a12, b12, a13, c13, b13 i/o ttl 8ma address/data bus: these leads are the time-multi- plexed address (lower eight bits only) and data bus for accessing the qe1m memory locations. upad7 is the most significant bit. high is logic 1. sel 146 b8 i ttl select: an active low signal generated by the micro- processor for accessing the qe1m memory loca- tions. rd 147 d7 i ttl read: an active low signal generated by the micro- processor for reading the qe1m memory locations. the memory map is selected by placing a low on the select lead. wr 148 c7 i ttl write: an active low signal generated by the micro- processor for writing to qe1m memory locations. the memory map is selected by placing a low on the select lead. ale 149 a7 i ttl address latch enable: an active high signal gen- erated by the microprocessor for holding an address stable during a read or write cycle. rdy 122 a15 o(t) ttl 8ma ready: a high is an acknowledgment from the addressed memory location that the transfer can be completed. a low indicates that the mapper cannot complete the transfer cycle, and that microproces- sor wait states must be generated. int 152 d6 o(t) ttl 8ma interrupt: a high or low on this output lead signals an interrupt request to the microprocessor. the polarity of this signal is determined by the state of the intsh lead. symbol 160-lead pqfp lead no. 208-lead pbga lead no. i/o/p type name/function
qe1m txc-04252 - 18 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. microprocessor bus interface - split bus for motorola (m) or intel (i) intsh 150 b7 i ttl interrupt sense high selection: a high on this lead causes the interrupt sense to be high when an interrupt occurs. a low causes the interrupt sense to be low when an interrupt occurs. note 1: leads upa(10-8) are implemented as input/output type ttl 4ma to support production tests but are used as ttl inputs. symbol 160-lead pqfp lead no. 208-lead pbga lead no. i/o/p type name/function a(10-0) 1, 160, 159, 158, 156, 153, 144, 143, 141, 140, 135 c3, b2, a2, a3, b5, c6, c8, d8, c9, b9, b10 i (note 1) ttl (note 1) address bus (motorola/intel buses): these address line inputs are used for accessing a qe1m memory loca- tion for a read/write cycle. a10 is the most significant bit. high is logic 1. d(7-0) 133, 132, 130, 129, 128, 126, 125, 124 d11, c11, c12, a12, b12, a13, c13, b13 i/o ttl 8ma data bus (motorola/intel buses): bidirectional data lines used for transferring data to or from a qe1m mem- ory location. d7 is the most significant bit. high is logic 1. sel 146 b8 i ttl select: a low enables data transfers between the micro- processor and the qe1m memory during a read/write cycle. rd / rd/wr 147 d7 i ttl read (i mode) or read/write (m mode): intel mode - an active low signal generated by the micro- processor for reading the qe1m memory locations. motorola mode - an active high signal generated by the microprocessor for reading the qe1m memory locations. an active low signal is used to write to memory locations. wr / lds 148 c7 i ttl write (i mode) or device select (m mode): intel mode - an active low signal generated by the micro- processor for writing to the qe1m memory locations. motorola mode - the sel and lds inputs are logically or-gated inside the qe1m, generating an internal active low select signal (cs ) that is similar to sel . this internal signal is used to enable data transfer. this lead can be used for the interface with the motorola 68302 micropro- cessor. if it is not used, it should be tied to ground, so that cs is the same signal as sel . symbol 160-lead pqfp lead no. 208-lead pbga lead no. i/o/p type name/function
qe1m txc-04252 - 19 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. controls, external clock and test leads rdy / dtack 122 a15 o(t) ttl 8ma ready (i mode) or data transfer acknowledge (m mode): intel mode - a high is an acknowledgment from the addressed qe1m memory location that the transfer can be completed. a low indicates that the mapper cannot complete the transfer cycle, and that microprocessor wait states must be generated. motorola mode - during a read bus cycle, a low signal indicates that the information on the data bus is valid. during a write bus cycle, a low signal acknowledges the acceptance of data. this lead is tristated. int/ irq 152 d6 o(t) ttl 8ma interrupt: when intsh is high, a high on this output lead signals an interrupt request int to the microproces- sor, as required for intel. when intsh is low, a low sig- nals an interrupt request irq to the microprocessor, as required for motorola. intsh 150 b7 i ttl interrupt sense high: interrupt polarity select. a high on this lead causes the interrupt sense to be high when an interrupt occurs. a low causes the interrupt sense to be low when an interrupt occurs. this lead must be set to meet the interrupt polarity requirement of the micropro- cessor. note 1: leads a(10-0) are implemented as type input/output type ttl 4ma to support production tests but are used as ttl inputs. symbol 160-lead pqfp lead no. 208-lead pbga lead no. i/o/p type name/function test 121 c14 i cmos transwitch test lead: a low must be placed on this lead. test 145 a8 i ttlp transwitch test lead: this lead is pulled high internally by an internal pull-up to v dd . it must be left floating or held high. extck 138 d10 i cmos external reference clock: this clock is used for desyn- chronizer operation and other purposes. the clock fre- quency must be 58.32 mhz (+/- 30 ppm over life) and the clock duty cycle must be (50 +/- 10) %. reset 155 c5 i ttl hardware reset: when an active low pulse is applied to this lead for a minimum duration of 150 nanoseconds after power is applied, this pulse clears all performance counters and alarms, resets the control bits (except those bits that force a high impedance state for the add buses), and initializes the internal fifos and internal spot pro- cessor. the microprocessor must write the control bit states for normal operation. symbol 160-lead pqfp lead no. 208-lead pbga lead no. i/o/p type name/function
qe1m txc-04252 - 20 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. boundary scan interface signals highz 136 a10 i ttl high impedance select: a low forces all output leads to the high impedance state for testing purposes (except tdo). abust 157 a4 i ttl add bus timing select: a low selects the a and b add bus clock, spe and c1j1v1 input signals for deriving tim- ing for the a and b add buses. a high selects the like-named drop bus for deriving timing (e.g., a drop bus for a add bus). this control lead is disabled when a 1 is written to control bit sbten. symbol 160-lead pqfp lead no. 208-lead pbga lead no. i/o/p type name/function tck 39 r2 i ttl ieee 1149 . 1 test port serial scan clock: this sig- nal is used to shift data into tdi on the rising edge, and out of tdo on the falling edge. the maximum clock frequency is 10 mhz. tms 36 n2 i ttlp ieee 1149.1 test port mode select: tms is sam- pled on the rising edge of tck, and is used to place the test access port controller into various states as defined in ieee 1149.1. this lead is set high inter- nally by an internal pull-up to v dd for normal framer operation. tdi 38 r1 i ttlp ieee 1149.1 test port serial scan data in: serial test instructions and data are clocked into this lead on the rising edge of tck. this input has an internal pull-up to vdd. tdo 37 p1 o(t) ttl 4ma ieee 1149.1 test port serial scan data out: serial test instructions and data are clocked out of this lead on the falling edge of tck. when inactive, this 3-state output will be put into its high impedance state. trs 35 n1 i ttlp ieee 1149.1 test port reset lead: this lead will asynchronously reset the test access port (tap) controller. this lead is to be held low, asserted low or pulsed low (for a minimum duration of 20 ns) to reset the tap controller on qe1m power-up. this input has an internal pull-up to v dd . symbol 160-lead pqfp lead no. 208-lead pbga lead no. i/o/p type name/function
qe1m txc-04252 - 21 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. absolute maximum ratings and environmental limitations notes: 1. conditions exceeding the min or max values may cause permanent failure. exposure to conditions near the min or max values for extended periods may impair device reliability. 2. pre-assembly storage in non-drypack conditions is not recommended. please refer to the instructions on the ? caution ? label on the drypack bag in which devices are supplied. 3. absolute value tested per mil-std-883d, method 3015.7. thermal characteristics the thermal characteristics of the pqfp and pbga versions of the qe1m device are shown in the table below: power requirements parameter symbol min max unit conditions supply voltage v dd -0.5 +6.0 v note 1 dc input voltage v in -0.5 v dd + 0.5 v note 1 storage temperature range t s -55 150 o cnote 1 ambient operating temperature t a -40 85 o c 0 ft/min linear airflow moisture exposure level me 5 level per eia/jedec jesd22-a112-a relative humidity, during assembly rh 30 60 % note 2 relative humidity, in-circuit rh 0 100 % non-condensing esd classification esd absolute value 2000 v note 3 latch-up lu jedec std-17 parameter min typ max unit test conditions thermal resistance: junction to ambient for pqfp -- -- 41.4 o c/w 0 ft/min linear airflow thermal resistance: junction to ambient for pbga -- -- 38 o c/w 0 ft/min linear airflow parameter min typ max unit test conditions v dd 4.75 5.0 5.25 v i dd 110 143 ma sts-1 power dissipation, p dd 550 750 mw sts-1 i dd 136 170 ma stm-1 or sts-3 power dissipation, p dd 680 900 mw stm-1 or sts-3
qe1m txc-04252 - 22 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. input, output and input/output parameters input parameters input parameters for cmos input parameters for ttl input parameters for ttlp parameter min typ max unit test conditions v ih 0.7 * v dd v4.75 v dd 5.25 v il 0.3 * v dd v4.75 v dd 5.25 input capacitance 7.5 pf parameter min typ max unit test conditions v ih 2.0 v 4.75 v dd 5.25 v il 0.8 v 4.75 v dd 5.25 input capacitance 7.5 pf parameter min typ max unit test conditions v ih 2.0 v 4.75 v dd 5.25 v il 0.8 v 4.75 v dd 5.25 input capacitance 7.5 pf input resistance 70 k ?
qe1m txc-04252 - 23 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. output parameters output parameters for cmos 4ma output parameters for ttl 4ma output parameters for ttl 8ma parameter min typ max unit test conditions v oh v dd - 0.7 v v dd = 4.75; i oh = -4.0 v ol 0.4 v v dd = 4.75; i ol = 4.0 i ol 4.0 ma i oh -4.0 ma input capacitance 7.5 pf parameter min typ max unit test conditions v oh 2.4 v v dd = 4.75; i oh = -4.0 v ol 0.4 v v dd = 4.75; i ol = 4.0 i ol 4.0 ma i oh -4.0 ma input capacitance 7.5 pf parameter min typ max unit test conditions v oh 2.4 v v dd = 4.75; i oh = -8.0 v ol 0.4 v v dd = 4.75; i ol = 8.0 i ol 8.0 ma i oh -8.0 ma input capacitance 7.5 pf
qe1m txc-04252 - 24 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. input/output parameters input/output parameters for ttl 4ma input/output parameters for ttl 8ma parameter min typ max unit test conditions v ih 2.0 v 4.75 v dd 5.25 v il 0.8 v 4.75 v dd 5.25 input capacitance 5.5 pf v oh 2.4 v v dd = 4.75; i oh = -4.0 v ol 0.4 v v dd = 4.75; i ol = 4.0 i ol 4.0 ma i oh -4.0 ma input capacitance 7.5 pf parameter min typ max unit test conditions v ih 2.0 v 4.75 v dd 5.25 v il 0.8 v 4.75 v dd 5.25 v oh 2.4 v v dd = 4.75; i oh = -8.0 v ol 0.4 v v dd = 4.75; i ol = 8.0 i ol 8.0 ma i oh -8.0 ma input capacitance 7.5 pf
qe1m txc-04252 - 25 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. timing characteristics detailed timing diagrams for the qe1m device are illustrated in figures 5 through 17, with values of the timing intervals tabulated below the waveform diagrams. the tristate condition of a signal waveform is shown as mid- way between high and low. the timing parameters are measured at voltage levels of (v ih + v il )/2 for input sig- nals or (v oh +v ol )/2 for output signals, unless otherwise indicated. where a waveform diagram describes both a and b bus signals, their symbols are combined in labeling the waveform (e.g., a/badd for aadd and badd ). figure 5. ports 1, 2, 3 and 4 e1 transmit timing notes: 1. tcin is shown for tclki = 0, where data is clocked in on falling edges. data is clocked in on rising edges when tclki =1. 2. for nrz operation, tnin is not used for data input and may instead be used as the input for an external active low loss of signal indication tlosn . otherwise, this lead must be held high. parameter symbol min typ max unit tcin clock period t cyc 488.28 ns tcin clock low time t pwl 150 ns tcin clock high time t pwh 150 ns tpin/tnin data setup time before tcin t su 10 ns tpin/tnin data hold time after tcin t h 2.0 ns t cyc t pwh t pwl t su t h tcin (input) tpin/tnin (input) note: n = 1 - 4
qe1m txc-04252 - 26 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 6. ports 1, 2, 3 and 4 e1 receive timing note: rcon is shown for rclki=0, where data is clocked out on rising edges. data is clocked out on falling edges when rclki=1. note: all output times are measured with a maximum 75 pf load capacitance. parameter symbol min typ max unit rcon clock period t cyc 480 498 ns rcon clock low time (rclki = 0) t pwl 257 ns rcon clock high time (rclki = 0) t pwh 222 241 ns rcon clock low time (rclki = 1) t pwl 222 241 ns rcon clock high time (rclki = 1) t pwh 257 ns rpon/rnon data delay after rcon t od 2.0 5.0 ns t cyc t pwl t pwh t od rcon (output) rpon/rnon (output) note: n = 1 - 4
qe1m txc-04252 - 27 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 7. sts-1 a/b drop and add bus signals, timing derived from drop bus note: for illustration purposes, a single tu/vt (tu number 21) is shown. the v1 pulse may or may not be present. if it is not present, the h4 byte must be provided. an additional byte time of delay in a/ba(7-0) is provided when control bit abd is written with a 1. the table omits a/b parameter prefixes. dspe edges are at payload boundaries. parameter symbol load min typ max unit dclk clock period t cyc 154.32 ns dlck duty cycle t pwh /t cyc 40 50 60 % d(7-0)/dpar data /parity setup time before dclk t su(1) 10 ns d(7-0)/dpar data /parity hold time after dclk t h(1) 5.0 ns dspe setup time before dclk t su(2) 10 ns dspe hold time after dclk t h(2) 5.0 ns dc1j1v1 setup time before dclk t su(3) 10 ns dc1j1v1 hold time after dclk t h(3) 5.0 ns dind drop bus indication output delay from dclk t d(1) 25pf 7.0 30 ns a(7-0)/apar data /parity out valid delay from dclk t od(2) 75pf 9.0 39 ns a(7-0)/apar data /parity to tristate delay from dclk t od(3) 8.0 20 ns add add indicator delay from dclk t od(1) 25pf 9.0 30 ns aind add bus indication output delay from dclk t od(4) 9.0 30 ns a(7-0)/apar data /parity out tristate to driven delay from dclk t od(5) 75pf 7.0 9.0 ns note: all output times are measured with the specified load capacitance. t cyc t h(2) a/bdclk (input) a/bd(7-0) (input) a/bdspe (input) a/bdc1j1v1 (input) a/bdind (output) a/ba(7-0) (output) a/badd (output) a/baind (output) t pwh t su(1) t h(1) t su(2) t su(3) t h(3) t d(1) t od(2) t od(3) t od(1) t od(4) a1 a2 c1 data data tu/vt selected j1 data data c1 j1 v1 tu/vt selected add bus tu/vt time slot when enabled drop bus tu/vt time slot when enabled occurs every four frames when provided in place of the h4 byte t od(5) a/bdpar a/bapar
qe1m txc-04252 - 28 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 8. stm-1/sts-3 a/b drop and add bus signals, timing derived from drop bus note: a single tu/vt is shown for illustration purposes. it also shows the tu/vt selection for the drop bus and add bus (number 21 in sts-1 number 3). the format is an au-3/sts-3. for vc-4 operation, one j1 pulse and one optional v1 pulse are present. an additional byte time of delay in a/ba(7-0) is provided when control bit abd is written with a 1. the table omits a/b parameter prefixes. dspe edges are at payload boundaries. parameter symbol load min typ max unit dclk clock period t cyc 51.44 ns dclk duty cycle t pwh /t cyc 40 50 60 % d(7-0)/dpar data /parity setup time before dclk t su(1) 10 ns d(7-0)/dpar data /parity hold time after dclk t h(1) 5.0 ns dspe setup time before dclk t su(2) 10 ns dspe hold time after dclk t h(2) 5.0 ns dc1j1v1 setup time before dclk t su(3) 10 ns dc1j1v1 hold time after dclk t h(3) 5.0 ns dind drop bus indication output delay from dclk t d(1) 25pf 7.0 30 ns a(7-0)/apar data /parity out valid delay from dclk t od(2) 75pf 9.0 39 ns a(7-0)/apar data /parity to tristate delay from dclk t od(3) 8.0 20 ns add add indicator delay from dclk t od(1) 25pf 9.0 30 ns aind add bus indication output delay from dclk t od(4) 9.0 30 ns a(7-0)/apar data /parity out tristate to driven delay from dclk t od(5) 75pf 7.0 9.0 ns note: all output times are measured with the specified load capacitance. t h(2) a/baind (output) t pwh t su(1) t h(1) c1(1) a/badd (output) a/ba(7-0) (output) a/bdind (output) a/bdc1j1v1 (input) a/bdspe (input) a/bdclk (input) c1(2) c1(3) data tu/vt selected j1 byte sts-1 #1 sts-1 #2 sts-1 #3 data sts-1 #1 j1 sts-1 #2 j1 sts-1 #3 v1 sts-1 #1 j1 sts-1 #1 c1(1) tu/vt selected add bus tu/vt time slot drop bus tu/vt time slot selected when enabled occurs every four frames when provided in place of the h4 byte selected when enabled t su(3) t h(3) t cyc t su(2) t d(1) t od(2) t od(3) t od(1) t od(4) t od(5) a/bd(7-0) (input) a/bdpar apar
qe1m txc-04252 - 29 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 9. sts-1 a/b add bus signals, timing derived from add bus notes: for illustration purposes, a single tu/vt is shown. the location of this tu/vt corresponds to tu/vt number 21. an additional byte time of delay in a/ba(7-0) is provided when control bit abd is written with a 1. the table omits a/b parameter prefixes. aspe edges are at payload boundaries. parameter symbol load min typ max unit aclk clock period t cyc 154.32 ns aclk duty cycle, t pwh /t cyc 40 50 60 % ac1j1v1 setup time before aclk t su(1) 10 ns ac1j1v1 hold time after aclk t h(1) 5.0 ns aspe setup time before aclk t su(2) 10 ns aspe hold time after aclk t h(2) 5.0 ns a(7-0)/apar data /parity out valid delay from aclk t od(2) 75pf 7.0 31 ns a(7-0)/apar data /parity to tristate delay from aclk t od(3) 7.0 16 ns add add indicator delayed from aclk t od(1) 25pf 7.0 24 ns aind add bus indication output delay from aclk t od(4) 7.0 24 ns a(7-0)/apar data /parity out tristate to driven delay from aclk t od(5) 75pf 5.0 7.0 ns note: all output times are measured with the specified load capacitance. t cyc t h(2) a/baclk (input) a/baspe (input) a/bac1j1v1 (input) a/ba(7-0) (output) a/badd (output) a/baind (output) t pwh t su(2) t su(1) t h(1) t od(2) t od(3) t od(1) t od(4) c1 j1 v1 tu/vt selected add bus tu/vt time slot when enabled occurs every four frames when provided t od(5) a/bapar
qe1m txc-04252 - 30 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 10. stm-1/sts-3 a/b add bus signals, timing derived from add bus note: a single tu/vt is shown for illustration purposes. it also shows the tu/vt selection for the drop bus and add bus (number 21 in sts-1 number 3). the format is an au-3/sts-3. for vc-4 operation, one j1 pulse and one optional v1 pulse are present. an additional byte time of delay in a/ba(7-0) is provided when control bit abd is written with a 1. the table omits a/b parameter prefixes. aspe edges are at payload boundaries. parameter symbol load min typ max unit aclk clock period t cyc 51.44 ns aclk duty cycle, t pwh /t cyc 40 50 60 % ac1j1v1 setup time before aclk t su(1) 10 ns ac1j1v1 hold time after aclk t h(1) 5.0 ns aspe setup time before aclk t su(2) 10 ns aspe hold time after aclk t h(2) 5.0 ns a(7-0)/apar data /parity out valid delay from aclk t od(2) 75pf 7.0 31 ns a(7-0)/apar data /parity to tristate delay from aclk t od(3) 7.0 16 ns add add indicator delayed from aclk t od(1) 25pf 7.0 31 ns aind add bus indication output delay from aclk t od(4) 7.0 31 ns a(7-0)/apar data /parity out tristate to driven delay from aclk t od(5) 75pf 5.0 7.0 ns note: all output times are measured with the specified load capacitance. t h(2) a/baind (output) t pwh a/badd (output) a/ba(7-0) (output) a/bac1j1v1 (input) a/baspe (input) a/baclk (input) j1 sts-1 #2 j1 sts-1 #3 v1 sts-1 #1 j1 sts-1 #1 c1(1) tu/vt selected add bus tu/vt time slot occurs every four frames when enabled selected when enabled t su(1) t h(1) t cyc t su(2) t od(2) t od(3) t od(1) t od(4) v1 sts-1 #2 v1 sts-1 #3 t od(5) a/bapar
qe1m txc-04252 - 31 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 11. microprocessor read cycle timing - multiplex bus parameter symbol min typ max unit ale pulse width t pw(1) 20 ns upa(10-8) and upad(7-0) address setup time before ale t su(1) 5.0 ns upa(10-8) and upad(7-0) address hold time after ale t h(1) 3.0 ns upa(10-8) and upad(7-0) address hold time after rd t h(2) 2.0 ns upad(7-0) data output delay to tristate after rd t od(1) 2.0 11 ns ale wait time after rd t w(1) 0.0 ns sel setup before rd t su(2) 0.0 ns sel hold time after rd t h(3) 0.0 ns rd wait after ale t w(2) 20 ns rd pulse width t pw(2) 40 ns rdy delay after sel t d(1) 2.0 10 ns rdy delay after rd t d(2) 4.0 20 ns rdy float time after sel t f(1) 2.0 10 ns address data t w(2) t pw(2) t su(2) t od(2) t h(3) t w(1) t pw(1) t h(1) t od(1) t h(2) t su(1) ale upa(10-8)* sel rd t pw(3) t d(2) t f(1) rdy (input) upad(7-0) (input/output) (input) (input) (output) t d(1) * address input only t od(3) t od(4) tristate tristate
qe1m txc-04252 - 32 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. notes: 1. all output times are measured with a maximum 75 pf load capacitance. 2. one spcyc equals two extck clock cycles. (the extck clock frequency is 58.32 mhz. one spcyc is about 34.29 ns.) 3. excessive external microprocessor data ram access could interfere with the qe1m internal data processing, result- ing in data corruption. to prevent such a situation, when excessive external microprocessor data ram access is detected, qe1m tries to slow down the external microprocessor access rate by lengthening the rdy pulse width to as high as 97 * spcyc. rdy pulse width register cycle t pw(3) 0.0 ns spot instruction read (note 2) 6 * spcyc 7 * spcyc ns data ram read (note 3) 9 * spcyc 33 * spcyc ns upad(7-0) data output delay after rd register read only t od(2) 8.0 28 ns upad(7-0) data output delay after rdy spot instruction read and data ram read only t od(3) 0.0 ns upad(7-0) data output tristate to driven delay after rd t od(4) 2.0 ns parameter symbol min typ max unit
qe1m txc-04252 - 33 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 12. microprocessor write cycle timing - multiplex bus parameter symbol min typ max unit ale pulse width t pw(1) 20 ns ale wait after wr t w(1) 0.0 ns upa(10-8) and upad(7-0) address setup time before ale t su(1) 5.0 ns upa(10-8) and upad(7-0) address hold time after ale t h(1) 3.0 ns upad(7-0) data input setup time before wr t su(2) 12 ns upad(7-0) data input hold time after wr t h(2) 6.0 ns sel setup time before wr t su(3) 0.0 ns sel hold time after wr t h(3) 0.0 ns wr wait after ale t w(2) 20 ns wr pulse width t pw(2) 40 ns rdy delay after sel t d(1) 2.0 10 ns rdy delay after wr t d(2) 4.0 20 ns rdy float time after sel t f(1) 2.0 10 ns t w(1) t pw(1) t h(1) t h(2) t h(3) t su(3) t w(2) t pw(2) t su(1) ale upa(10-8)* sel wr address data t su(2) t pw(3) t d(2) t d(1) t f(1) rdy (input) upad(7-0) (input) (input) (input) (output) * address input only t su(4)
qe1m txc-04252 - 34 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. notes: 1. all output times are measured with a maximum 75 pf load capacitance. 2. one spcyc equals two extck clock cycles. (the extck clock frequency is 58.32 mhz. one spcyc is about 34.29 ns.) 3. excessive external microprocessor data ram access could interfere with the qe1m internal data processing, result- ing in data corruption. to prevent such a situation, when excessive external microprocessor data ram access is detected, qe1m tries to slow down the external microprocessor access rate by lengthening the rdy pulse width to as high as 97 * spcyc. rdy pulse width register write t pw(3) 0.0 ns spot instruction write (note 2) 5 * spcyc 7 * spcyc ns data ram write (note 3) 9 * spcyc 29 * spcyc ns data valid set up time to wr spot instruction write and data ram write only t su(4) -1 * spcyc ns parameter symbol min typ max unit
qe1m txc-04252 - 35 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 13. microprocessor read cycle timing - intel parameter symbol min typ max unit a(10-0) address setup time to sel t su(1) 0.0 ns a(10-0) address hold time after rd t h(1) 3.0 ns d(7-0) data output float time after rd t f(1) 2.0 11 ns sel setup time to rd t su(2) 10 ns rd pulse width t pw(1) 40 ns sel hold time after rd t h(2) 0.0 ns rdy delay after sel t d(2) 2.0 10 ns rdy delay after rd t d(3) 4.0 20 ns rdy float time after sel t f(2) 2.0 10 ns t su(1) a(10-0) d(7-0) sel rd rdy t su(2) t pw(1) t pw(2) t d(3) t d(2) t f(2) t h(2) t d(1) t f(1) t h(1) (input) (output) (input) (input) (output) t d(4) t d(5) address data
qe1m txc-04252 - 36 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. notes: 1. all output times are measured with a maximum 75 pf load capacitance. 2. one spcyc equals two extck clock cycles. (the extck clock frequency is 58.32 mhz. one spcyc is about 34.29 ns.) 3. excessive external microprocessor data ram access could interfere with the qe1m internal data processing, result- ing in data corruption. to prevent such a situation, when excessive external microprocessor data ram access is detected, qe1m tries to slow down the external microprocessor access rate by lengthening the rdy pulse width to as high as 97 * spcyc. rdy pulse width register read t pw(2) 0.0 ns spot instruction read (note 2) 6 * spcyc 7 * spcyc ns data ram read (note 3) 9 * spcyc 33 * spcyc ns data output valid delay after rd register read only t d(1) 8.0 28 ns data output valid delay after rdy spot instruction read and data ram read only t d(4) 0.0 ns data output tristate to driven delay after rd t d(5) 2.0 ns parameter symbol min typ max unit
qe1m txc-04252 - 37 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 14. microprocessor write cycle timing - intel notes: 1. all output times are measured with a maximum 75 pf load capacitance. 2. one spcyc equals two extck clock cycles. (the extck clock frequency is 58.32 mhz. one spcyc is about 34.29 ns.) 3. excessive external microprocessor data ram access could interfere with the qe1m internal data processing, result- ing in data corruption. to prevent such a situation, when excessive external microprocessor data ram access is detected, qe1m tries to slow down the external microprocessor access rate by lengthening the rdy pulse width to as high as 97 * spcyc. parameter symbol min typ max unit a(10-0) address setup time to sel t su(1) 0.0 ns a(10-0) address hold time after wr t h(1) 3.0 ns d(7-0) data input valid setup time to wr t su(2) 12 ns d(7-0) data input hold time after wr t h(2) 6.0 ns sel setup time to wr t su(3) 10 ns wr pulse width t pw(1) 40 ns rdy delay after sel t d(1) 2.0 10 ns rdy delay after wr t d(2) 4.0 20 ns rdy float time after sel t f 2.0 10 ns rdy pulse width register write t pw(2) 0.0 ns spot instruction write (note 2) 5 * spcyc 7 * spcyc ns data ram write (note 3) 9 * spcyc 29 * spcyc ns d(7-0) data valid setup time to wr spot instruction write and data ram write only t su(4) -1 * spcyc ns t su(1) a(10-0) d(7-0) sel wr rdy t su(4) t su(2) t pw(2) t f t h(2) t h(1) t pw(1) t d(2) t d(1) t su(3) (input) (input) (input) (input) (output) address data
qe1m txc-04252 - 38 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 15. microprocessor read cycle timing - motorola parameter symbol min typ max unit a(10-0) address setup time and rd/wr setup time before cs t su(1) 10 ns a(10-0) address hold time and rd/wr delay time after cs t h(1) 3.0 ns d(7-0) data output float time after cs t f(1) 2.0 11 ns cs pulse width t pw(1) 40 ns dtack driven delay after sel t d(2) 2.0 10 ns dtack float time after sel t f(2) 2.0 10 ns dtack stable delay after address becomes stable (note 4) t d(3) 6.0 26 ns dtack pulse width register read t pw(3) 0.0 ns spot instruction read (note 2) 6 x spcyc 7 x spcyc ns data ram read (note 3) 9 x spcyc 33 x spcyc ns d(7-0) data output delay after cs register read only t d(1) 8.0 28 ns d(7-0) data output delay after dtack spot instruction read and data ram read only t d(4) 0.0 ns d(7-0) data output tristate to drive delay after cs t d(5) 2.0 ns t su(1) t pw(1) t f(1) t pw(3) t h(1) t f(2) t d(1) t d(2) a(10-0) d(7-0) sel rd/wr dtack cs t d(3) note: cs is an internal signal which is the logical or of the sel and lds lead input signals. (input) (input) (output) (internal) (input) (output) its timing parameters refer to whichever of these signals controls the associated transition. t d(4) t d(5) address data
qe1m txc-04252 - 39 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. notes: 1. all output times are measured with a maximum 75 pf load capacitance. 2. one spcyc equals two extck clock cycles. (the extck clock frequency is 58.32 mhz. one spcyc is about 34.29 ns.) 3. excessive external microprocessor data ram access could interfere with the qe1m internal data processing, result- ing in data corruption. to prevent such a situation, when excessive external microprocessor data ram access is detected, qe1m tries to slow down the external microprocessor access rate by lengthening the dtack pulse width to as high as 97 x spcyc. to avoid such delays the following are transwitch recommendations for access frequency for the qe1m spot data ram (addresses are shaded in the memory map at the end of the data sheet). a. use 16 wait states for a read or write access if the dtack signal is not being used. forcing a longer wait state for every access may create unwanted delays in the internal process for the qe1m. using the 16 wait states will provide reliability without causing excessive process delays (at the 25 mhz microprocessor frequency). for other frequencies, use an equivalent number of wait states that equals approximately 640 ns. b. maintain no more than 16 microprocessor accesses per 125 s frame period. c. maintain a minimum of 600 ns between microprocessor accesses. 4. during a spot instruction read or data ram read cycle, dtack stays high after t d(3) . during a register read cycle, dtack settles to low after t d(3 ) . dtack may go directly from a low to a high impedance state.
qe1m txc-04252 - 40 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 16. microprocessor write cycle timing - motorola parameter symbol min typ max unit a(10-0) address setup time and rd/wr setup time before cs t su(1) 10 ns a(10-0) address hold time and rd/wr delay time after cs t h(1) 3.0 ns d(7-0) data input setup time before cs t su(2) 12 ns d(7-0) data input hold time after cs t h(2) 6.0 ns cs pulse width t pw(1) 40 ns dtack driven delay after sel t d(2) 2.0 10 ns dtack float time after sel t f 2.0 10 ns dtack stable delay after address becomes stable (note 4) t d(3) 6.0 26 ns dtack pulse width register write t pw(3) 0.0 ns spot instruction write (note 2) 5 x spcyc 7 x spcyc ns data ram write (note 3) 9 x spcyc 29 x spcyc ns d(7-0) data valid setup time to cs spot instruction write and data ram write only t su(3) -1 x spcyc ns t su(1) t pw(1) t pw(3) t h(1) t f t d(2) a(10-0) d(7-0) sel rd/wr dtack cs t su(3) t su(2) t h(2) t d(3) note: cs is an internal signal which is the logical or of the sel and lds lead input signals. (input) (input) (input) (internal) (input) (output) its timing parameters refer to whichever of those signals controls the associated transition. address data
qe1m txc-04252 - 41 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. notes: 1. all output times are measured with a maximum 75 pf load capacitance. 2. one spcyc equals two extck clock cycles. (the extck clock frequency is 58.32 mhz. one spcyc is about 34.29 ns.) 3. excessive external microprocessor data ram access could interfere with the qe1m internal data processing, result- ing in data corruption. to prevent such a situation, when excessive external microprocessor data ram access is detected, qe1m tries to slow down the external microprocessor access rate by lengthening the dtack pulse width to as high as 97 x spcyc. to avoid such delays the following are transwitch recommendations for access frequency for the qe1m spot data ram (addresses are shaded in the memory map at the end of the data sheet). a. use 16 wait states for a read or write access if the dtack signal is not being used. forcing a longer wait state for every access may create unwanted delays in the internal process for the qe1m. using the 16 wait states will provide reliability without causing excessive process delays (at the 25 mhz microprocessor frequency). for other frequencies, use an equivalent number of wait states that equals approximately 640 ns. b. maintain no more than 16 microprocessor accesses per 125 s frame period. c. maintain a minimum of 600 ns between microprocessor accesses. 4. during a spot instruction write or data ram write cycle, dtack stays high after t d(3) . during a register write cycle, dtack settles to low after t d(3 ). dtack may go directly from a low to a high impedance state.
qe1m txc-04252 - 42 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 17. boundary scan timing note 1: the output time (tdo) is measured with a maximum of 75 pf load capacitance. parameter symbol min max unit tck clock high time t pwh 50 ns tck clock low time t pwl 50 ns tms setup time before tck t su(1) 3.0 - ns tms hold time after tck t h(1) 2.0 - ns tdi setup time before tck t su(2) 3.0 - ns tdi hold time after tck t h(2) 2.0 - ns tdo delay from tck (note 1) t d -22ns trs pulse width t pw(1) 20 - ns tms tdi tdo t d tck (input) (input) (input) (output) t h(2) t su(2) t su(1) t h(1) t pwh t pwl t pw(1) t pw(1) trs (input)
qe1m txc-04252 - 43 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. operation the following sections detail the internal operation of the quad e1 mapper. bus interface modes the quad e1 mapper supports the following bus modes of operation: - drop mode - single unidirectional ring mode - multiplexer mode - dual unidirectional ring mode drop mode in the drop mode of operation, a tu/vt is terminated from either the a or b drop bus to the receive output of one of the four ports, without a return path in the transmit direction. single unidirectional ring mode in the single unidirectional ring mode of operation, a tu/vt is dropped from the a (or b) drop bus, with the return path the a (or b) add bus. timing for the tu/vt to be added to the a (or b) add bus is derived from either the a (or b) drop bus, or from the a (or b) add bus. multiplexer mode in the multiplexer mode of operation, a tu/vt is dropped from the a (or b) drop bus, with the return path the b (or a) add bus. timing for the tu/vt to be added to the a (or b) add bus is derived from either the a (or b) drop bus, or from the a (or b) add bus. dual unidirectional ring mode in the dual unidirectional ring mode of operation, a tu/vt is dropped from the a (or b) drop bus, with the return path both the a and b add buses. timing for the tu/vt to be added to the a (or b) add bus is derived from either the a (or b) drop bus, or from the a (or b) add bus.
qe1m txc-04252 - 44 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. bus mode selection tu/vt bus mode selection is performed by the control bits defined in the table shown below. the n represents the port number (1-4). note: both the a and b add buses power up in the high impedance state. a 0 must be written to control bits aahze and bahze for normal add bus operation. bus mode selection for port n sdh/sonet add/drop multiplexing format selections the control bit settings for format selection are given in the table shown below. when the sts-1 format is selected, the buses are configured to operate at a bus rate of 6.48 mbyte/s, instead of 19.44 mbyte/s for vc-4/au-3/sts-3 formats. format selection mode type tnsel1 tnsel0 rnsel drop from bus add to bus dropping only, from a 0 0 0 a drop-only (1) dropping only, from b 0 0 1 b drop-only (1) adding only, to a 0 1 0 add-only (2) a adding only, to b 0 1 1 add-only (2) b single unidirectional ring 0 1 0 a a single unidirectional ring 0 1 1 b b multiplexer, a in, b out 1 0 0 a b multiplexer, b in, a out 1 0 1 b a dual unidirectional ring 1 1 0 a a and b dual unidirectional ring 1 1 1 b b and a notes: 1. when the drop-only mode is selected, the ability to add a tu/vt is disabled, and the add bus is tri-stated. 2. the add-only feature is enabled by writing a 1 to control bit frdisn. the febe value and rdi states are trans- mitted as zero. however, the microprocessor can send an rdi, if required. format mod1 mod0 sts-1 format 0 0 sts-3 format 0 1 stm-1 au-3 format 1 0 stm-1 tug-3/vc-4 format 1 1
qe1m txc-04252 - 45 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. drop tu/vt selection the tu-12 (vt2) number selection register labels (rtunn), which consist of seven bits, are given in the fol- lowing table. an out of range value forces a high impedance state at the e1 receive interface. in addition, the febe and rdi states will be transmitted as zeros. tu/vt selection locations 04ch (port 1), 07ch (port 2), 0ach (port 3), 0dch (port 4) bit6543210 au-3/tug-3 or sts-1 id tu/vt group number tu/vt number meaning 0000000 no tu/vt selected 00 sts-1 0 1 au-3/tug-3 a, sts-1 #1 1 0 au-3/tug-3 b, sts-1 #2 1 1 au-3/tug-3 c, sts-1 #3 0 0 1 tu/vt group number 1 0 1 0 tu/vt group number 2 0 1 1 tu/vt group number 3 1 0 0 tu/vt group number 4 1 0 1 tu/vt group number 5 1 1 0 tu/vt group number 6 1 1 1 tu/vt group number 7 00 no tu/vt selected 0 1 tu/vt number 1 1 0 tu/vt number 2 1 1 tu/vt number 3
qe1m txc-04252 - 46 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. add tu/vt selection the tu-12 (vt2) number selection register labels (ttunn), which consist of seven bits, are given in the follow- ing table. an out of range value forces a high impedance state on the add bus. tu/vt selection locations 04dh (port 1), 07dh (port 2), 0adh (port 3), 0ddh (port 4) bit6543210 au-3/tug-3 or sts-1 id tu/vt group number tu/vt number meaning 0000000 no tu/vt selected 00 sts-1 0 1 au-3/tug-3 a, sts-1 #1 1 0 au-3/tug-3 b, sts-1 #2 1 1 au-3/tug-3 c, sts-1 #3 0 0 1 tu/vt group number 1 0 1 0 tu/vt group number 2 0 1 1 tu/vt group number 3 1 0 0 tu/vt group number 4 1 0 1 tu/vt group number 5 1 1 0 tu/vt group number 6 1 1 1 tu/vt group number 7 0 0 no tu/vt selected 0 1 tu/vt number 1 1 0 tu/vt number 2 1 1 tu/vt number 3
qe1m txc-04252 - 47 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. bus timing timing for adding a tu/vt to the add bus is derived from the like-named drop bus, or from the like-named add bus. bus timing may be selected by using a lead, or through software. upon power-up or a device reset, the sbten (software bus timing enable) control bit is reset to 0 and the abust lead controls bus timing selec- tion. to enable the software to control timing, the sbten control bit must be first written with a 1, which will override the state placed on the abust lead. when sbten is 1, bus timing (add or drop bus timing) is con- trolled by the drpbt control bit. the various states associated with the bus timing selection are shown in the table below. bus timing selection unequipped operation the qe1m is capable of sending an unequipped channel or unequipped supervisory channel in all add modes of operation. generally a channel which has either the uchne bit or both the uchne and uschne bits set in the port provisioning registers will add an unequipped channel or unequipped supervisory channel for the tu/vt selected. an unequipped channel has a tu/vt pointer consisting of a valid ndf, size bits equal to 01, and a fixed pointer value of 105. the remaining vt overhead bytes and the payload are sent as zeros. the unequipped supervisory channel has an identical pointer to the unequipped channel, but sends a valid j2 byte, and valid bip-2 bits and rdi-bit in v5, and valid rdi-bits in z7. the qe1m also sends a valid z6 byte. the v5, rdi, z7 rdi, and z6 bytes can be set to zero by other control bits if they are not required. there are some dif- ferences in operation based on the ueame bit in register 014h. the following table describes these differ- ences. abust lead sbten drpbt action low 0 x add bus timing selected by abust lead. high 0 x drop bus timing selected by abust lead. x 1 0 add bus timing selected by drpbt bit. x 1 1 drop bus timing selected by drpbt bit. note: x = don ? t care
qe1m txc-04252 - 48 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. unequipped channel generation uchne/uschne ueame add/drop mode drop from a add b add 0x 1 mux a high-z normal b normal high-z single unidirectional ring a normal high-z b high-z normal bidirectional ring a normal normal b normal normal drop only ahigh-zhigh-z bhigh-zhigh-z 1 0 mux a unequipped 2 normal b normal unequipped 2 single unidirectional ring a unequipped high-z b high-z unequipped bidirectional ring a unequipped unequipped b unequipped unequipped drop only ahigh-zhigh-z bhigh-zhigh-z 1 mux a high-z unequipped 2 b unequipped 2 high-z single unidirectional ring a unequipped high-z b high-z unequipped bidirectional ring a unequipped unequipped b unequipped unequipped drop only ahigh-zhigh-z bhigh-zhigh-z notes: 1. x = don ? t care (0 or 1). 2. only multiplexed mode is effected by the ueame control bit. all other modes operate the same way regardless of the state of the ueame control bit.
qe1m txc-04252 - 49 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. drop bus multiframe alignment v1 byte alignment in the receive direction (from the drop bus) is established by using the h4 byte or the v1 ref- erence pulse in the adc1j1v1 and bdc1j1v1 signal. depending on the format, one or three v1 pulses will be present in this signal. when the h4 byte is used to establish v1 byte alignment, the v1 pulse does not have to be present in the adc1j1v1 or bdc1j1v1 signal. writing a 1 to control bit dv1sel selects the v1 pulse in the adc1j1v1 and bdc1j1v1 signal to be used to establish the v1 byte location reference, while a 0 selects the h4 byte as the multiframe detector for establishing the v1 reference. the h4 multiframe detection circuits are disabled when the v1 pulse is used in place of the h4 byte. for stm-1 vc-4 operation, a single v1 pulse must occur three drop bus clock cycles every four frames follow- ing the j1 pulse. for stm-1 au3/sts-3 operation, three v1 pulses must be present every four frames. each v1 pulse must be present three clock cycles after the corresponding j1 pulse, when the spe signal is high. for example, in a vc-4 signal, the j1 pulse identifies the j1 byte location (defined as the starting location for the vc-4) in the poh bytes. in the next column (first clock cycle) all the rows are assigned as fixed stuff. similarly, in the next column (second clock cycle) all the rows are assigned as fixed stuff. the next column (third clock cycle) defines the start of tug-3 a. this column is where the v1 pulse occurs every four frames. however, the actual v1 byte occurs six clock cycles after the v1 pulse. for sts-1 operation, one v1 pulse must be present. the v1 pulse must occur on the next clock cycle after j1, and when the spe signal is high. the j1 pulse identifies the j1 byte location (defined as the starting location for the sts-1) in the poh bytes. the next column (first clock cycle) defines the vts starting location. thus, the v1 pulse identifies the starting location of the first v1 byte in the signal. the rest of the v1 bytes for the 21 vt2s are also aligned with respect to the v1 pulse. the timing relationships between j1, v1, and other signals are shown in the timing characteristics section. the h4 byte is used to identify the location of the v1 byte as shown in 18 below: figure 18. h4 byte floating vt mode bit allocation the h4 byte is monitored for multiframe alignment when enabled. loss of multiframe alignment is declared (asdh4e, bsdh4e) if two or more h4 byte values differ from those of a 2-bit counter for two consecutive mul- tiframes. recovery occurs when four consecutive sequential h4 byte values are detected once. v1 35 bytes v2 35 bytes v3 35 bytes v4 35 bytes 2048 kbit/s tu/vt h4 (xxxx xx00) of previous spe h4 (xxxx xx01) h4 (xxxx xx10) h4 (xxxx xx11)
qe1m txc-04252 - 50 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. add bus multiframe alignment when drop bus timing is selected, add bus v1 alignment is based on the drop bus v1 pulse (a/bdc1j1v1) if dv1sel is 1, or on the v1 reference signal that is generated by the h4 multiframe detectors in the drop bus side if dv1sel is 0. when add bus timing is selected and a 0 is written to control bit dv1ref, v1 byte alignment for the add bus is established by using the v1 pulses that must be present in the a/bac1j1v1 signal. when add bus timing is selected and a 1 is written to control bit dv1ref, v1 byte alignment for the add bus is determined by the drop bus v1 reference from either the a/bdc1j1v1 signal (if dv1sel is 1), or from the internal v1 reference signal generated by the h4 multiframe detector in the drop bus direction (if dv1sel is 0). the v1 pulse that is present in the a/bac1j1v1 signal is ignored. extreme care must be taken when using this v1 selection mode to prevent add bus v1 byte alignment slips. the control bit selection for both v1 add and drop bus byte alignment is described in the table below. add and drop bus v1 reference selection bus timing mode dv1ref dv1sel action drop bus timing selected 0 0 drop bus a/b h4 multiframe detector determines dropped tu/vt v1 byte starting location, and added tu/vt v1 byte starting location. v1 pulse in drop bus a/bdc1j1v1 signal ignored. drop bus timing selected 0 1 drop bus v1 pulse in the a/bdc1j1v1 signal determines dropped tu/vt v1 byte starting location, and added tu/vt v1 byte starting location. a/b drop bus h4 multiframe detec- tor disabled. add bus timing selected 0 0 drop bus a/b h4 multiframe detector determines dropped tu/vt v1 byte starting location. v1 pulse in drop bus a/bdc1j1v1 signal ignored. add bus v1 alignment deter- mined by the v1 pulse in the add bus a/bac1j1v1 signal. add bus timing selected 0 1 drop bus v1 pulse in the a/bdc1j1v1 signal determines dropped tu/vt starting location. drop bus h4 multiframe detector disabled. add bus v1 alignment determined by the v1 pulse in the add bus a/bac1j1v1 signal. add bus timing selected 1 0 drop bus a/b h4 multiframe detector determines dropped tu/vt v1 byte starting location. v1 pulses in drop bus a/bdc1j1v1 and add bus a/bac1j1v1 signals are ignored. add bus v1 alignment determined by the internal v1 pulse generated by the drop bus a/b h4 byte detector. add bus timing selected 1 1 drop bus v1 pulse in the a/bdc1j1v1 signal determines dropped tu/vt v1 byte starting location, a/b drop bus h4 multiframe detector disabled. v1 pulse in add bus a/bac1j1v1 signal is ignored. add bus v1 alignment deter- mined by the v1 pulse in the drop bus a/bdc1j1v1 signal. note: x = don ? t care. bus timing mode is selected via lead abust and control bits sbten, drpbt, as described earlier.
qe1m txc-04252 - 51 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. performance counters all performance counters are saturating, with the counters stopping at their maximum count. a counter is reset to zero by a hardware or software device reset, and when it is read by the microprocessor. the performance counters for port n are also reset when a 1 is written to control bit rnsetc. this bit is self-clearing, and does not require the microprocessor to write a 0 into its location. counts that occur during the read cycle are held and updated afterwards. for a 16-bit counter, the low order byte must be read first, followed by reading the high order byte before the corresponding low order byte for another port is read. alarm structure all alarm indications are reported as unlatched and latched status bits. the latched bit of an alarm can be set on the positive transitions, negative transitions, both positive and negative transitions, or positive levels of the alarm. reading a latched alarm bit clears the bit to 0. when control bit laten (address 011h, bit 4) is written with a 1, the latching of alarm transitions is enabled. control bits ipos and ineg (address 012h, bits 5 and 4) should be programmed to select the transition(s) on which latched bits are set. when laten is written with a 0, the latched bits are set on positive levels of the alarms. the ipos and ineg bits are disabled when laten is set to 0. alarm hierarchy mask since multiple alarms at various levels can be detected simultaneously, a hierarchical masking scheme is employed in the qe1m. the qe1m hierarchical mask effectively eliminates the confusion caused by the simul- taneous reporting of multiple alarms and speeds up the identification of the alarm origins. the following table shows the hierarchical masking of unlatched low level alarms by high order alarms (depending on the drop bus selected and the port selected). masked cells indicate the lower level alarm masked by the high order alarms. for example: low level alarms j2lol and j2tim are masked when any of the following high order alarms/conditions are active: dloc, oor, uaisi, dh4e, ais, lop or sler. notes: 1. oor: receive tu/vt out of range is the condition when the receive tu/vt select bits (registers 0x4c, 7c, ac, dc) are set to an invalid value in which no tu/vt is selected (e.g. 0x00). there is no alarm bit to indicate this condition. 2. when control bit heaise is 1 3. when control bit dv1sel is 0 4. when control bit tcnen is 1 5. when control bit 1bnrdi = 0 when control bit 1bnrdi = 1, then j2 message tracking is still enabled and sler alarm will not mask j2lol and j2tim. high order alarms or conditions low level alarms masked by high order alarms uaisi dh4e lop ais ndf size sler rfi uneq j2lol j2tim rdis rdip rdic tcuq tcais tclm tcll tctm tcodi tcrdi dloc oor 1 uaisi 2 , dh4e 3 ais, lop signal label =001 or =000 sler 5 tclm 4
qe1m txc-04252 - 52 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. interrupt structure the interrupt indication register (address 020h) contains the global software interrupt bit int and other inter- rupt indication bits. each interrupt indication bit has an associated set of latched alarm bits. a mask bit is pro- vided to enable the set of latched alarms to trigger their interrupt indication bit. for port alarms, the latched alarms of each port are further divided into several groups. a second level of mask bit is provided for each of these groups to mask out the interrupt indication bit of the port. for each interrupt indication bit, if its interrupt mask bits are 1, and one or more of its associated latched alarm bits are set, the interrupt indication bit will become 1; which in turn causes the software interrupt indication bit int to become 1. the qe1m also gener- ates a hardware interrupt at the tristate 8ma interrupt lead int(int/irq ), lead 152 or d6, provided the hard- ware interrupt enable bit (hwdie) is 1. addresses 016h and 021h are the first set of interrupt mask registers. the additional mask registers for the port alarms are contained in addresses 017h, 018h and 019h. upon power-up, when the reset bit (bit 7 in address 015h) is written with a 1, or an active low is placed on the reset lead (lead 155 or c5), all the inter- rupt mask bits are cleared to 0. they must be initialized to 1 in order to enable the interrupt indication bits. con- trol bits ipos, ineg and laten should also be programmed to determine how the latched alarms are to be set. consider alarm anais. assume that hwdie is 1, the interrupt masks for anais are 1, the control bits ipos and laten are 1, and control bit ineg is 0. since anais is a port alarm, interrupt mask bit pnmsk and the second level mask bit rptna should be set to 1. a positive transition on anais causes the latched bit of anais to be set, which in turn sets the interrupt indication bit portn. then, both software and hardware interrupts occur. when an interrupt occurs, the external microprocessor can determine the alarm that caused the interrupt by reading the latched alarm registers that correspond to the interrupt indication bit and interrupt mask bit. the read cycles allow the microprocessor to determine what alarm has been set. when the register containing the latched alarm (e.g., anais) has been read, the latched alarm bit is cleared, releasing the software interrupt (int and portn returning to 0) and hardware interrupt. if there is more than one alarm in more than one alarm register, each of the corresponding latched alarm registers must be read before the interrupt is released. in addition, the hardware and software interrupt may be released by writing a 0 to the mask bits that correspond to the interrupt indication register. for anais, the interrupt can be masked by writing 0 to pnmsk or to the rptna bits.
qe1m txc-04252 - 53 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. interrupt registers address interrupt indication register (address 020h) 020h int extck aside bside port4 port3 port2 port1 interrupt mask register (address 016h, 021h) 016h 0 000000sptmsk 021h 0 eckmsk asmsk bsmsk p4msk p3msk p2msk p1msk additional interrupt mask registers (addresses 017h, 018h, 019h) 017h rpt4a rpt4b rpt3a rpt3b rpt2a rpt2b rpt1a rpt1b 018h tfifo4a tfifo4b tfifo3a tfifo3b tfifo2a tfifo2b tfifo1a tfifo1b 019h tport4 tport3 tport2 tport1 rfifo4 rfifo3 rfifo2 rfifo1 interrupt indication aside registers (addresses 022h, 024h) a side drop/add alarms (aside) 022h adloc aaloc adpar 0 0 a3uaisi a2uaisi a1uaisi 024h lextc 0 0 0 0 a3dh4e a2dh4e a1dh4e interrupt indication bside registers (addresses 026h, 028h) b side drop/add alarms (bside) 026h bdloc baloc bdpar 0 0 b3uaisi b2uaisi b1uaisi 028h sptloc wdtexp 0 perr 0 b3dh4e b2dh4e b1dh4e interrupt indication portn registers (addresses 030h, 04eh, 05ah, 03ah, 05eh, 05ch, 044h for port 1) port n alarms (portn) 030h 060h 090h 0c0h anais anlop ansize anndf anrdis anrfi anuneq ansler 04eh 07eh 0aeh 0deh anrdip anrdic 0 0 anj2lol anj2tim 0 0 05ah 08ah 0bah 0eah antcuq antcais antclm antcll antctm antcodi antcrdi 0 03ah 06ah 09ah 0cah bnais bnlop bnsize bnndf bnrdis bnrfi bnuneq bnsler 05eh 08eh 0beh 0eeh bnrdip bnrdic 0 0 bnj2lol bnj2tim 0 0 05ch 08ch 0bch 0ech bntcuq bntcais bntclm bntcll bntctm bntcodi bntcrdi 0 044h 074h 0a4h 0d4h rnffe 0 1 tanfe tbnfe tnlos tnloc tndais
qe1m txc-04252 - 54 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. alarms, interrupt masks and interrupt indications a side and b side alarms and interrupts latched alarm address alarm name interrupt mask or (016h or 021h) additional interrupt mask (if any) interrupt indication bit (020h) 022h adloc asmsk aside aaloc adpar 0 0 a3uaisi a2uaisi a1uaisi 024h lextc eckmsk extck 0 0 0 0 a3dh4e asmsk aside a2dh4e a1dh4e 026h bdloc bsmsk - bside baloc bdpar 0 0 b3uaisi b2uaisi b1uaisi 028h sptloc sptmsk - (note 1) wdtexp 0 perr 0 b3dh4e bsmsk - bside b2dh4e b1dh4e note 1. the spot alarm does not have an interrupt indication bit but it can still cause both software interrupt (int bit) and hardware interrupt (int/irq lead).
qe1m txc-04252 - 55 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. a side and b side port n alarms and interrupts latched alarm address alarm name interrupt mask (021h) additional interrupt mask (if any) (017h) interrupt indication bit (020h) latched alarm address alarm name interrupt mask (021h) additional interrupt mask (if any) (017h) interrupt indication bit (020h) 030 port 1 060 port 2 090 port 3 0c0 port 4 anais pnmsk rptna portn 03a port 1 06a port 2 09a port 3 0ca port 4 bnais pnmsk rptnb portn anlop bnlop ansize bnsize anndf bnndf anrdis bnrdis anrfi rfie (note 1) bnrfi rfie (note 1) anuneq rptna bnuneq rptnb ansler bnsler 04e port 1 07e port 2 0ae port 3 0de port 4 anrdip 05e port 1 08e port 2 0be port 3 0ee port 4 bnrdip anrdic bnrdic 00 00 anj2lol bnj2lol anj2tim bnj2tim 00 00 05a port 1 08a port 2 0ba port 3 0ea port 4 antcuq 05c port 1 08c port 2 0bc port 3 0ec port 4 bntcuq antcais bntcais antclm bntclm antcll bntcll antctm bntctm antcodi bntcodi antcrdi bntcrdi 00 note 1. rfie (address 012h, bit 3) is a common control bit for all four ports. a 1 enables the rfi indication to cause an interrupt. rptna or rptnb is not required to be set to 1 to enable the interrupt for the rfi indication. a 0 disables an rfi indication from causing an interrupt.
qe1m txc-04252 - 56 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. common port n alarms and interrupts latched alarm address alarm name interrupt mask (021h) additional interrupt mask (if any) (018h or 019h) interrupt indication bit (020h) 044 port 1 074 port 2 0a4 port 3 0d4 port 4 rnffe pnmsk rfifon portn 0 1 tanfe tfifona tbnfe tfifonb tnlos tportn tnloc tndais
qe1m txc-04252 - 57 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. interrupt and alarm control bit summary ipos 012h: 5 ineg 012h: 4 hwdie 014h: 0 laten 011h: 4 interrupt mask bit action on an alarm 0 0 0 1 x no alarm event indication, or interrupt register indication. x x x 0 0 alarm event register sets on positive levels of an alarm; no software or hardware interrupt indications. x x 0 0 1 alarm event register sets, and software inter- rupt indication occurs, on positive levels of the alarm; no hardware interrupt. x x 1 0 1 alarm event register sets, and software and hardware interrupt indications occur, on posi- tive levels of the alarm. 1 0 x 1 0 alarm event register sets on positive transi- tions of the alarm; no software or hardware interrupt indications. 1 0 0 1 1 alarm event register sets, and software inter- rupt indication occurs, on positive transitions of the alarm; no hardware interrupt. 1 0 1 1 1 alarm event register sets, and software and hardware interrupt indications occur, on posi- tive transitions of the alarm. 0 1 x 1 0 alarm event register sets on negative transi- tions of the alarm; no software or hardware interrupt indications. 0 1 0 1 1 alarm event register sets, and software inter- rupt indication occurs, on negative transitions of the alarm; no hardware interrupt. 0 1 1 1 1 alarm event register sets, and software and hardware interrupt indications occur, on nega- tive transitions of the alarm. 1 1 x 1 0 alarm event register sets on positive and/or negative transitions of the alarm; no software or hardware interrupt indications. 1 1 0 1 1 alarm event register sets, and software inter- rupt indication occurs, on positive and/or neg- ative transitions of the alarm; no hardware interrupt. 1 1 1 1 1 alarm event register sets, and software and hardware interrupt indications occur, on posi- tive and/or negative transitions of alarm.
qe1m txc-04252 - 58 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. sdh/sonet ais detection the quad e1 mapper can detect an upstream ais condition using the toh h1/h2 (pointer) bytes or the toh e1 (order wire) byte. when control bit se1ais (address 014h, bit 3) is 0, the h1/h2 bytes are monitored for an upstream ais condition. when the mod control bits (address 010h, bits 7 and 6) select the vc-4/tug-3 for- mat, the h11 and h21 bytes only are monitored for ais. the monitoring of ais in the two other h1n/h2n bytes is disabled. when the mod control bits select the sts-3 or au-3 format, each set of the three h1/h2 bytes per a drop and b drop buses are monitored for an ais indication. each of the three h1/h2 pointer bytes corre- sponds to the like-numbered au-3/sts-1 signal (n=1-3). when the mod control bits select the sts-1 format, the h1/h2 bytes per a drop and b drop buses are monitored for an ais indication. if all ones are detected in the h1/h2 bytes (whose location is determined by the c1 pulse) for three consecu- tive frames, the alarm bits asuaisi in addresses 022h and 023h (a bus detected h1/h2 or e1 byte upstream ais) or bsuaisi in addresses 026h and 027h (b bus detected h1/h2 or e1 byte upstream ais) will set. recovery occurs when a normal ndf (bits 1 through 4) in h1 is detected for three consecutive frames. a nor- mal ndf is defined as a 0110, but 1110, 0010, 0100 and 0111 are also recognized as normal. the h1/h2 byte ais detection circuits (when selected) for both the a and b drop buses are disabled by writing a 0 to control bit heaise (address 013h, bit 7). when control bit se1ais is 1, the e1n bytes are monitored for an upstream ais condition. when the mod con- trol bits select the vc-4/tug-3 format, the e11 byte in both buses is monitored for ais. the detection of the upstream ais indication in the e12 and e13 bytes is disabled. when the mod control bits select the au-3/sts-3 format, each of the three e1n bytes in the a and b drop buses are monitored for ais. each of the three e1n bytes corresponds to the like-numbered au-3/sts-1 signal. for sts-1 operation, the single e1 byte is checked for the upstream ais indication. majority logic is used to determine if an e1n byte is carrying an upstream ais indication. if 5 or more ones (at least 5 bits equal to 1 out of the 8 bits) are detected once in a a/b drop bus e1n byte (whose locations are determined by the c1 pulse), the alarm bit asuaisi (a bus detected h1/h2 or e1 byte ais) or bsuaisi (b bus detected h1/h2 or e1 byte ais) is set. recovery occurs when 4 or more zeros (at least 4 bits equal to 0 out of the 8 bits) are detected once. the e1n byte ais detection circuits (when selected) for both the a and b drop buses are disabled by writing a 0 to control bit heaise.
qe1m txc-04252 - 59 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. tu/vt pointer tracking the starting location of the v1 byte is determined by either the v1 pulses in the a/bc1j1v1 signals or the h4 multiframe detection circuits. the tu/vt pointer bit assignment for the v1 and v2 bytes is shown below. the alignment is necessary to determine the starting locations of the v5 byte and the other bytes that are carrying the 2048 kbit/s format. i = increment bit d = decrement bit n = new data flag bit (enabled = 1001 or 0001/1101/1011/1000, normal or disabled = 0110 or 1110/0010/0100/0111) negative justification: inverted 5 d-bits and accept majority rule positive justification: inverted 5 i-bits and accept majority rule ss-bits (vt size) = 10 for 2048 kbit/s pointer bytes bit assignment the pointer value is a binary number with a range of 0 to 139 for the 2048 kbit/s format. the pointer offset indi- cates the offset from the v2 byte to the first byte in the tu-12/vt2 mapping. the pointer bytes are not counted in the offset calculation. the pointer offset arrangement for this format is shown below. tu/vt pointer offset locations v1 byte v2 byte 1234567812345678 nnnnss-bits ididididid v1 105 106-138 139 v2 0 1-33 34 v3 35 36-68 69 v4 70 71-103 104 2048 kbit/s tu-12/vt2
qe1m txc-04252 - 60 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. eight independent pointer-tracking state machines are used in the quad e1 mapper, one for each of the a and b buses in each of the four ports 1, 2, 3, and 4. the pointer tracking algorithm is illustrated in 19. the pointer tracking state machine is based on the pointer tracking machine found in the latest etsi requirements, and is also valid for both bellcore and ansi. when control bit ptalte at address 014h, bit 1 is 0, the transition from ais to lop is disabled (shown dotted), which is required in bellcore recommendations. figure 19. tu/vt pointer tracking state machine inc lop ais dec norm 3 x ais_ind (offset undefined) 3 x new_point (accept new offset) 3 x ais_ind (offset undefined) 3 x new_point (accept new offset) 3 x any_point dec_ind (decr. offset) 3 x new_point (accept new offset) 3 x new_point (accept new offset) 3 x any_point ndf_enable (accept new offset) 8 x inv_point (offset undefined) 3 x new_point (accept new offset) 3 x ais_ind (offset undefined) 8 x inv_point (offset undefined) ndf_enable (accept new offset) 3 x ais_ind (offset undefined) 8 x ndf_enable (offset undefined) ndf_enable (accept new offset) ndf_enable (accept new offset) ndf_enable (accept new offset) 3 x new_point (accept new offset) 3 x any_point inc_ind (incr. offset) 3 x ais_ind (offset undefined) ndf
qe1m txc-04252 - 61 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. remote defect indications a 1-bit/3-bit rdi selection bit - 1bnrdi (bit 4 in registers 048h, 078h, 0a8h, 0d8h) - has been added to allow the user to select between the enhanced 3-bit rdi (1bnrdi = 0) or single bit rdi (1bnrdi = 1). the following sections describe the differences. v5 and k4 (z7) byte coding (for 3-bit rdi) bits 5, 6 and 7 in the k4 (z7) byte, in conjunction with bit 8 in the v5 byte, provide a detection scheme which is compliant with earlier versions of the rdi standard and also with enhanced tu/vt rdi capability. the enhanced version of rdi allows the user to differentiate between server, connectivity, and payload defects. bit 8 in v5 is set equal to bit 5 in k4 (z7). bit 7 in k4 (z7) is set to the inverse of bit 6 of k4 (z7) to distinguish the enhanced version of rdi from the old version of rdi. it should be noted that when bits 6 and 7 in k4 (z7) are either 01 or 10, the rdi indication is also influenced by bit 8 of v5, as shown in the table below. when bits 6 and 7 are either 00 or 11, then rdi is determined solely by bit 8 in v5. this allows detection of an rdi originat- ing from older equipment that generates the rdi in the v5 byte. the following table lists the rdi defect indica- tions carried in the v5 and k4 (z7) bytes. rdi bit assignment for 3-bit rdi bit 8 v5 bit 5 k4 (z7) bit 6 k4 (z7) bit 7 k4 (z7) definition 0 0 0 no defect indications. 0 0 1 no defect indications. 0 1 0 remote payload defect - path label mismatch - loss of multiframe. 0 1 1 no defect indications. 1 0 0 remote defect (old equipment). 1 0 1 remote server defect - vt loss of pointer - vt ais detected - upstream ais detected (e1 or h1/h2 bytes). 1 1 0 remote connectivity defect - unequipped signal label - j2 mismatch - j2 loss of lock 1 1 1 remote defect (old equipment).
qe1m txc-04252 - 62 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. receive rdi detection and recovery (for 3-bit rdi) the rdi alarms are defined in the table below. the number of consecutive events for detection and recovery is controlled by control bit v5al10 in address 014h, bit 2. the value of five is selected when the v5al10 control bit is 0, and the value of ten is selected when the v5al10 control bit is 1. rdi alarm definition for 3-bit rdi transmit rdi generation (for 3-bit rdi) an rdi is sent for the following unlatched alarm conditions in the v5 and k4 (z7) overhead bytes of the vt added to the a or b add bus, depending on the states of the rnsel (active bus selected), tnsel1 and tnsel0 (bus enabled) control bits. the following examples apply to port 1, but corresponding examples for ports 2 through 4 may be constructed by substituting the port number digit for the 1-digit in the bit symbols (except dv1sel). the variable s refers to the sts-1 or au-3/tug-3 identifier (s = 1 - 3). - when rdi enable (rdien) is 1, a remote server defect indication is sent for: - vt loss of pointer (a1lop, b1lop) - vt ais (a1ais, b1ais) - a/b drop bus upstream ais in h1/h2 or the e1 byte (asuaisi, bsuaisi), when heaise is 1 - microprocessor writes a 1 to t1rdis - when rdi enable (rdien) is 1, a remote payload defect indication is sent for: - a/b drop h4 error (asdh4e, bsdh4e), when dv1sel is 0 - mismatch signal label (a1sler, b1sler) - microprocessor writes a 1 to t1rdip - when rdi enable (rdien) is 1, a remote connectivity defect indication is sent for: - unequipped signal label (a1uneq, b1uneq), when uqae is 1 - j2 mismatch (a1j2tim, b1j2tim), when j21aise is 1 - j2 loss of lock (a1j2lol, b1j2lol), when j21aise is a 1 - microprocessor writes a 1 to t1rdic - when rdi enable (rdien) is 0, the microprocessor can control rdi generation: - microprocessor writes a 1 to t1rdis to generate remote server defect indication. - microprocessor writes a 1 to t1rdip to generate remote payload defect indication. - microprocessor writes a 1 to t1rdic to generate remote connectivity defect indication. note:the microprocessor may send an rdi by writing to the above control bits at any time, including the add-only mode. to prevent contention between the internal logic and full microprocessor control, the rdien control bit should be written with a 0 when microprocessor control is intended. the priority used for sending rdi if more than one of the microprocessor controls are set is: server, connectivity, and payload. when rdien = 1 and no defects are gen- erated then k4 bits 5,6,7 = 001. anrdic bnrdic anrdip bnrdip anrdis bnrdis action 0 0 1 remote server defect indication, and old equip- ment rdi indication (bit 8 in the v5 byte). 0 1 0 remote payload defect indication. 1 0 0 remote connectivity indication.
qe1m txc-04252 - 63 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. v5 and k4 (z7) byte coding (for 1-bit rdi) in the receive (rx) direction bit 8 in the v5 byte is used to detect remote defect indications. bits 5, 6, and 7 in the rx k4(z7) byte are not looked at for detecting rdi and can have any incoming value, 0 or 1. for transmitting 1-bit rdi, bit 8 in v5 byte will be set as shown below and bits 5,6,7 in the k4(z7) byte will be sent as 0. see table below: rdi bit assignment for 1-bit rdi receive rdi detection and recovery (for 1-bit rdi) the rdi alarm is defined in the table below. the number of consecutive events for detection and recovery is controlled by a common register - provisioning control bit v5al10 (register 014h, bit 2). when v5al10 = 0, the value is 5; when v5al10 = 1, the value is 10. a remote defect indication is indicated by alarm indication bit anrdis/bnrdis. alarm indication bits anrdip/bnrdip and anrdic/bnrdic are disabled and will always be equal to zero when 1-bit rdi mode is selected. rdi alarm definition for 1-bit rdi transmit rdi generation (for 1-bit rdi) an rdi is sent for the following unlatched alarm conditions in the v5 overhead byte of the vt added to the a or b add bus, depending on the states of the rnsel (active bus selected), tnsel1 and tnsel0 (bus enabled) control bits. the following examples apply to port 1, but corresponding examples for ports 2 through 4 may be constructed by substituting the port number digit for the 1-digit in the bit symbols (except dv1sel). the vari- able s refers to the sts-1 or au-3/tug-3 identifier (s = 1 - 3). - when rdi enable (rdien) is 1, a remote defect indication (bit 8 in v5=1; bits 5,6,7 in k4(z7)=0) is sent for: - vt loss of pointer (anlop, bnlop) - vt ais (anais, bnais) - a/b drop bus upstream ais in h1/h2 or the e1 byte (asuaisi, bsuaisi), when heaise is 1. - unequipped signal label (anuneq, bnuneq), when uqae is 1. - j2 loss of lock (a1j2lol, b1j2lol), when j21aise is a 1. - j2 mismatch (a1j2tim, b1j2tim), when j21aise is 1 - microprocessor writes a 1 to t1rdis to generate a remote defect indication. bit 8 v5 bit 5 k4 (z7) bit 6 k4 (z7) bit 7 k4 (z7) definition 0 0 0 0 no defect indications. 1 0 0 0 remote defect indication. anrdic bnrdic anrdip bnrdip anrdis bnrdis action 0 0 0 no defect indications. 0 0 1 remote defect indication.
qe1m txc-04252 - 64 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. - when rdi enable (rdien) is 0, the microprocessor can control rdi generation: - microprocessor writes a 1 to t1rdis to generate remote defect indication. note: for 1-bit rdi mode the following unlatched alarm conditions will not generate a remote defect indica- tion: - a drop h4 error (asdh4e, bsdh4e), when dv1sel is a 0. - mismatch signal label (ansler, bnsler). note: for 1-bit rdi mode the following microprocessor control bits are disabled and will not generate a remote defect indication: - microprocessor writes a 1 to tnrdip. - microprocessor writes a 1 to tnrdic. overhead communications bit access microprocessor access is provided for the eight overhead communications bits (o-bits) carried in the two justi- fication control (jc) bytes in the multiframe format, e.g., in a 2048 kbit/s tu/vt, shown partially below. the bits in the justification control byte are numbered 1 through 8, starting with c1 as bit 1. o-bit placement in a 2048 kbit/s tu/vt in the receive direction, the eight o-bits are stored in eight 8-bit registers (a and b for each group of 4 ports) and these registers are updated each frame. the two o-bit nibbles that form a byte in the registers for receiv- ing and transmitting are from the same multiframe. bits 3 through 0 in an o-bit register correspond to bits 3 through 6 (c1c2 oooo rr) in the first justification control byte, and bits 7 through 4 in an o-bit register corre- spond to bits 3 through 6 in the second justification control byte, as shown below. o-bit assignment memory map other bytes j2 byte jc byte 1 c1 c2 o o o o r r 32 bytes - information rrrrrrrr n2 (z6) byte jc byte 2 c1 c2 o o o o r r other bytes second justification control byte first justification control byte bit34563456 register76543210
qe1m txc-04252 - 65 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. receive j2 byte processing there are two possible received j2 message sizes, 16 bytes (itu-t), or 64 bytes (ansi). the qe1m is capa- ble of dimensioning the transmit (and receive) ram memory segment to the two sizes (16-byte or 64-byte). in addition, two modes of operation are provided for the 16-byte (itu-t) format: a microprocessor read mode, and a compare read mode. the following table lists the various control states associated with j2 processing. the itu-t defined 16-byte message consists of an alignment signal of (10000000 00000000) in the most sig- nificant bit (bit 1) of the message. the remaining 7 bits in each byte carry a data message, as illustrated below. itu-t 16-byte j2 message format j2nsize j2ncom action 0 0 transmit and receive j2 segments are configured for the 16-byte j2 message size. microprocessor read for the dropped j2 mes- sage. j2 alarms are disabled. 0 1 transmit and receive j2 segments are configured for the 16-byte j2 message size. for receiving, a 16-byte microprocessor mes- sage is written into a 16-byte segment for comparison against the received message. the written message must start with the multi- frame indicator written into the starting location of the segment. 1 x transmit and receive j2 segments are configured for the 64-byte j2 message size. microprocessor read for the dropped j2 mes- sage. j2 alarms are disabled. the tandem connection feature must be disabled by setting tcnen=0 for the port. note: x = don ? t care bit12345678 1 16-byte j2 message 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
qe1m txc-04252 - 66 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. the definitions (itu-t) shown below will be used in the following discussion of the j2 16-byte message com- parison function. the memory locations apply to each memory group. the j2 16-byte message comparison works according to the following steps: 1. the microprocessor-written reference message (exti) locations should be initialized with the correct j2 16-byte message before enabling the j2 message comparison function. 2. the j2 message comparison function is then enabled (j2ncom = 1; j2nsize = 0) and immediately the j2 loss of lock alarm will be active (j2nlol = 1) and the j2 trace identifier mismatch alarm will be inactive (j2ntim = 0). this is the first step in the sequence - to initialize these alarms. 3. the incoming trace message (rxti) is received, and the j2 comparison circuit searches for the j2 align- ment pattern (bit 1: 1000...0 pattern). 4. j2 alignment pattern is found and the received stable trace message (acti) locations are updated with this incoming trace message (rxti). 5. the incoming trace message (rxti) is then checked for three consecutive 16-byte message repeats. 6. if an error occurs before step 5 is completed, the sequence repeats, starting at step 3 (searching for the alignment pattern). 7. if the incoming trace message (rxti) repeats three times in a row (after the alignment pattern is detected) without an error then this is an in-lock condition, and the j2 loss of lock alarm is reset (j2nlol = 0). note that at this time the j2 mismatch alarm is still inactive (j2ntim =0). 8. once the incoming trace message is in-lock, the stable message (acti), is compared against the micropro- cessor-written reference message (exti), byte for byte, for 16 bytes (the length of the multiframe mes- sage). if they compare (acti = exti), a match is declared, with no mismatch alarm (j2ntim = 0). if they do not compare (acti exti), a mismatch alarm is declared (j2ntim = 1). a j2 mismatch alarm results in rdi and receive line ais being sent continuously, when enabled. there is no loss of lock alarm (j2nlol = 0) because the incoming trace message (rxti) is stable. 10. if the incoming message (rxti) changes for three consecutive 16-byte messages, a loss of lock alarm (j2nlol = 1) occurs and the sequence starts again from the beginning (step 2). summary of j2 alarms: - j2 loss of lock (j2nlol) is a comparison between the received stable message (acti) and the receive incoming (real time) message (rxti). - declare lock (j2nlol = 0) when acti = rxti for 3 consecutive set of 16 bytes. - loss of lock (j2nlol = 1) when acti rxti on at least 1 byte in each of 3 consecutive 16-byte messages - j2 trace identifier mismatch (j2ntim) is a comparison between the received stable message (acti) and the microprocessor-written reference message (exti). - declare mismatch (j2ntim = 1) when acti exti on any byte once lock is declared. itu-t definitions e1mx16 definitions rxti - received tti (trail trace identifier) incoming j2 trace message (real time) exti - expected tti (trail trace identifier) microprocessor-written trace (reference) message. a side (x50h - x5fh) b side (xd0h - xdfh) acti - accepted tti (trail trace identifier) received stable trace message. a side (x40h - x4fh) b side (xc0h - xcfh)
qe1m txc-04252 - 67 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. - clear mismatch (j2ntim = 0) when acti = exti. see note below. note: a mismatch alarm is declared for the following reasons. 1. a valid mismatch alarm would be declared when the stable message (acti) does not match the reference message (exti). 2. an invalid mismatch alarm would be declared if the correct start-up procedure was not used and the refer- ence message (exti) was not loaded before enabling the j2 comparison function. 3. another reason for getting an invalid mismatch alarm would be if the reference message was written with the wrong message value. in any case if the incoming message is stable (or in-lock - j2nlol = 0) then the only way to clear the mis- match alarm would be to cause a loss of lock condition. suggested j2 16-byte message comparison start-up procedure: from start-up: 1) at transmitting device - send a ? valid ? message (txti). 2) at receive device - a) load microprocessor-written reference message (exti) with a ? valid ? message. b) enable j2 message comparison. note: 1 and 2 are interchangeable if changing messages: 1) at receive device - load microprocessor-written reference message (exti) with a ? new valid ? message. 2) at transmitting device - send a ? new valid ? message (txti). note: if 1 is not done before 2 then a mismatch alarm is declared. if this occurs it is not a valid mismatch (assuming that the messages are correct). following the start-up procedure above will assure that the trace identifier mismatch alarm only activates when the messages do not match. there is the possibility that a mismatch alarm will activate by not following the cor- rect start-up procedure, upon which the following should be done: 1) at receive device - verify that microprocessor-written (reference) message (exti) is correct 2) at receive device - verify that the stable message (acti) is correct by examining j2nlol. since acti is written only once at the beginning of the algorithm, when searching for the j2 alignment pattern, if no loss of lock alarm is set then the incoming message rxti is still the same valid message in acti. now force a loss of lock condition by using the microprocessor to overwrite any byte of the stable message (acti) with a value that corrupts the alignment pattern (i.e., address x40=0x00). the loss of lock alarm will set, and then the re-start the algorithm from the beginning, which resets the mismatch alarm, and starts searching again for the alignment pattern.
qe1m txc-04252 - 68 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. n2 (z6) overhead byte (tandem connection) the tandem connection feature is enabled for a tu/vt by writing a 1 to control bit tcnen, when control bit j2nsize is a 0. when control bit tcnen is written with a 0, the tandem connection feature is disabled. see address 051h, bit 4, in the memory map descriptions section for more detail on tcnen. the bit placement in a received n2 (z6) byte is as shown below: bip-2, ais indication, tc rei and tc oei processing one or two errors may be detected in the tc bip-2 comparison, and they are counted individually in an 8-bit counter when control bit block is written with a 0 (an tc bip-2 error counter, bn tc bip-2 error counter). when control bit block is written with a 1, one or two parity errors are counted as a single block error. a tandem connection ais alarm (antcais, bntcais) is declared when bit 4 is equal to 1 for five consecutive frames. recovery occurs when bit 4 is equal to 0 for five consecutive frames. an 8-bit counter (an tc rei counter, bn tc rei counter) is provided for counting the number of rei bits received as equal to 1 in bit 5 (tc rei) in the n2 (z6) byte. a rei indication (a 1) indicates that the distant end has detected one or two errors when the bip-2 calculated for frame f-1 (all the bytes) is compared against the bip-2 value carried in the n2 (z6) byte in frame f. an 8-bit counter (an tc oei counter, bn tc oei counter) is provided for counting the number of oei bits received as equal to 1 in bit 6 (tc oei) in the n2 (z6) byte. an oei indication (a 1) indicates that the distant end has detected one or two errors when the bip-2 calculated for frame f-1 is compared against the bip-2 value carried in the v5 byte in frame f. bits 7 and 8 a multiframe alignment pattern, trace identifier message, tc rdi and tc odi indications are assigned to bits 7 and 8 in the frames of a 76-frame structure, as shown below: bit12345678 bip-2 1 ais indication tc rei tc oei (febe) trace id tc rdi/odi frame no. n2 (z6) byte definition 1 - 8 frame alignment, 1111 1111 1111 1110 9 - 12 tc trace id byte no. 0 (1 c1 c2 c3 c4 c5 c6 c7) 13 - 16 tc trace id byte no. 1 (0 x x x x x x x) 17 - 20 tc trace id byte no. 2 (0 x x x x x x x) 21 - 24 thru 61 - 64 tc trace id bytes no. 3 thru 13 65 - 68 tc trace id byte no. 14 (0 x x x x x x x) 69 - 72 tc trace id byte no. 15 (0 x x x x x x x) 73 bit 7 = 0, bit 8 = tc rdi 74 bit 7 = tc odi, bit 8 = 0 75 bit 7 = 0, bit 8 = 0 76 bit 7 = 0, bit 8 = 0
qe1m txc-04252 - 69 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. loss of multiframe (status bits antclm, bntclm) occurs when four consecutive frame alignment signals (1111 1111 1111 1110) are detected in error (i.e., one or more error in each fas). multiframe alignment is recovered when three consecutive non-errored fas are found. the tc trace identifier message comparison is based on the same state machine as that used for the 16-byte j2 message. if the message is not locked, an antcll or bntcll alarm is declared. after tc lock is estab- lished, a comparison is performed between the microprocessor-written tc and the contents of the incoming message. the message consists of tc trace id bytes 0 to 15. a tc trace identifier mismatch (antctm, bntctm) alarm is declared when any byte does not match. recovery occurs when there is a match between the microprocessor message and the accepted message. bit 8 in frame 73 is defined as a tandem connection remote defect indication (tc rdi). a tc rdi alarm occurs when a 1 has been detected in bit 8 in frame 73 for 5 consecutive multiframes (where each multiframe is 38 ms). the tc rdi alarm state is exited when bit 8 is equal to 0 for 5 consecutive multiframes. an alarm indication is reported as antcrdi or bntcrdi. bit 7 in frame 74 is defined as a tandem connection outgoing defect indication (tc odi). a tc odi alarm occurs when a 1 has been detected in bit 7 in frame 74 for 5 consecutive multiframes (where each multiframe is 38 ms). the tc odi alarm state is exited when bit 7 is equal to 0 for 5 consecutive multiframes. an alarm indication is reported as antcodi or bntcodi. tandem connection unequipped status unequipped tandem connection detection is provided. five or more consecutive received tandem connection n2 (z6) bytes equal to xx00 0000 result in a tc unequipped indication (antcuq, bntcuq). the alarm state is exited when five or more consecutive received tandem connection n2 (z6) bytes are not equal to xx00 0000. note that bits 1 and 2 of the n2 (z6) byte are masked (shown as x) and do not affect the indication.
qe1m txc-04252 - 70 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. tug-3 null pointer indicator for stm-1 tug-3 format, the quad e1 mapper has the option to generate and transmit a null pointer indicator (npi) for one or more of the tug-3s, as shown below. npi structure three control bits (npia, npib and npic in address 010h, bits 2-0) are provided for selecting one or more of the tug-3 npis. the three control bits are enabled when the mod1 and mod0 control bits are 11 (tug-3/vc-4 format). the npi consists of three bytes, starting with row 1. the table below shows the bit assignment for the first two bytes. npi bit assignment the third npi byte is designated as fixed stuff and is transmitted as zero. the remaining cross-hatched bytes in the first two columns of the tug-3 are tristated on the add bus. when a 1 is written to control bit nullz in address 013h, bit 3 and the npi feature is enabled (i.e., npia, npib or npic is a 1) the bytes following the npi bytes are transmitted as zeros. when the nullz bit is a 0, the bytes following the npi bytes are tristated. bit12345678 row 110010011 row 211100000 n p i 261 86 vc-4 1 n p i 86 1 n p i 86 1 p o h 1 tug-3a tug-3b tug-3c
qe1m txc-04252 - 71 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. e1 loopback capability the qe1m provides two types of e1 loopbacks, called facility and line loopbacks (i.e., at the facility side and at the line side, as illustrated in 20). in 20, the e1 transmit data and clock goes into the qe1m, while the e1 receive data and clock comes out of the qe1m. facility loopback for port n, enabled when a 1 is written to control bit fnlbk, directs the incoming e1 transmit data and clock to the outgoing receive data and clock signal. line loopback for port n, enabled when a 1 is written to control bit lnlbk, routes the outgoing e1 receive data and clock signal (instead of the incoming e1 transmit data and clock) to the sdh/sonet transmitter. figure 20. facility and line loopbacks lnlbk anantx from desynchronizer hdb3 coder receive data & clock (nrz, rail) 0 1 fnlbk 0 1 bypasn 1 0 1 0 transmit data & clock (nrz, rail) prbs analyzer hdb3 coder bypasn 0 1 prbsnen 0 1 prbs generator to synchronizer nrz nrz xmit nrz rec nrc nrz rail line loopback facility loopback clock e1 line ananool ananen
qe1m txc-04252 - 72 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. prbs pattern generator and analyzer each port has a data generator and analyzer for 2 15 -1 prbs patterns, as illustrated in 20. the prbs genera- tor is enabled when a 1 is written to control bit prbsnen. the prbs pattern will be synchronous to the clock driving the hdb3 decoder. when a 1 is written to ananen control bit, the prbs analyzer is enabled. when control bit anantx is 0, the analyzer will sample the receive nrz clock and data (rec nrz) signals. when the control bit anantx is 1, the internal transmit nrz clock and data signals (xmit nrz) will be sampled by the analyzer. resets the quad e1 mapper has several reset options. these include a full hardware and software device reset, par- tial software resets, and counter software resets. all of the software reset bits are self-clearing (i.e., they do not require 0 to be written to a register location after the reset is applied by setting the bit to 1). note that the self-clearing function requires the presence of the clock signal provided to the extck lead (lead 138 or d10). upon power-up, when the reset bit (address 015h, bit 7) is written with a 1, or an active low signal is placed on the reset lead (lead 155 or c5), the add bus data and the port e1 interfaces are forced to a high imped- ance state until the device is initialized. the control bits aahze and bahze (address 010h, bits 5 and 4) must be written with zeros to enable the add bus interfaces. the rnen control bits must be programmed to 1 to acti- vate the line interfaces. in addition, the aaind , baind , aadd and badd leads are forced off. all performance counters are reset, and the alarms (except anlop and bnlop) are reset. the control bits (except those shaded in the memory map) are also forced to zero, and the various fifos are re-initialized. the shaded bits are contained in the data ram, and these can be initialized by writing a 1 to initsp (see memory map descriptions, address 015h, bit 0). a hardware reset can only be applied after the clocks are stable, and must be present for a minimum duration of 150 ns. writing a 1 to the rnsets software reset control bit for any of the ports resets the port n performance counters, re-initializes the fifo, and clears the alarms, except the anlop and bnlop alarms, which will set for port n. the loss of pointer alarms will recover when a valid pointer is received. the control bits will not be reset. writing a 1 to the rnsetc counter reset control bit for any of the ports reset the performance counters for that port. this feature allows the performance measurements to start at the same time for a port. writing a 1 to control bit restab (address 015h, bit 6) resets the alarms for the a bus and for lextc (i.e., addresses 022h to 025h). writing a 1 to control bit restbb (address 015h, bit 5) resets the alarms for the b bus and the spot alarms (i.e., addresses 026h to 028h). note that a hardware reset will automatically trigger all the software reset bits. software reset bit reset will trigger all rnsets, all rnsetc, restab and restbb automatically. a rnsets will also automatically trig- ger a rnsetc.
qe1m txc-04252 - 73 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. start-up procedure the following procedure should be followed to start up the qe1m in a known good state from initial power-on, or from a hardware or software reset. initial power-on: (start from step 1) from a hardware reset: (start from step 2) from a software reset: (start from step 4) (1) power up device (2) apply hardware reset (lead 155 or c5) (3) load spot microcode (see flowchart in figure 26) (4) apply software reset (reset=1; register 0x015 = 0x80) (5) initialize data ram (initsp=1; register 0x015 = 0x01) (6) load all control registers for user specific operation (7) clear any alarms that may have been latched, by generating the following resets: - restab and restbb (register 0x015 = 0x60) - r1sets (register 0x052 = 0x80) - r2sets (register 0x082 = 0x80) - r3sets (register 0x0b2 = 0x80) - r4sets (register 0x0e2 = 0x80) (8) clear anlop and bnlop by reading the corresponding port status registers: - clear a1lop (read register 0x030) - clear a2lop (read register 0x060) - clear a3lop (read register 0x090) - clear a4lop (read register 0x0c0) - clear b1lop (read register 0x03a) - clear b2lop (read register 0x06a) - clear b3lop (read register 0x09a) - clear b4lop (read register 0x0ca)
qe1m txc-04252 - 74 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. pointer leak rate calculations notes: 1. the procedure described in notes 2 through 8 below must be performed independently for each of the four ports of the qe1m device. 2. the procedure shown in the diagram above uses a ten-second sliding window with a resolution of one second. 3. the initial fifo leak rate register value (in memory map address 049h, 079h, 0a9h or 0d9h) must first be set to 04 hex. 4. measure ten consecutive one-second samples from the positive and negative stuff counters being used. store all ten difference values, i.e., s1 = pos stuff count1 - neg stuff count1, s2 = pos stuff count2 - neg stuff count2, and so on through s10 = pos stuff count10 - neg stuff count10. there are eight pairs of stuff counters in the qe1m; care should be taken to use the pair appropriate to the programmed configuration of the device. the counters are located at addresses 032h, 062h, 092h, 0c2h (a side) and 03ch, 06ch, 09ch, 0cch (b side). 5. calculate the leak rate (l.r.) using the following equation: l.r. = hex[ int [ 280 / c ] ], where c = abs [ s1 + s2 + ... + s10 ]. then, if l.r. < 4, let l.r. = 4, or if l.r. > 255, let l.r. = 255. 6. set the fifo leak rate register (address 049h, 079h, 0a9h or 0d9h) with the value between 4 and 255 calculated above, then take another one-second sample (e.g., s11). 7. recalculate the value of 'c' by subtracting the oldest sample and adding the newest, and calculate a new leak rate, as described in note 5 (e.g., using s2 through s11). 8. continue to repeat the steps described in notes 5, 6 and 7 until ais, lop, los or ndf is received or until you reset the qe1m. measure 1 second subt oldest add newest calculate leak rate measure 1 second, add to c set fifo leak rate set fifo leak rate 10 sec 10 sec ais, lop los, ndf or reset to 04 hex (note 6) (note 7) (note 6) (note 5) fifo (note 4) (note 3) start
qe1m txc-04252 - 75 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. jitter measurements equipment used in qe1m jitter measurements: hewlett-packard digital transmission analyzer:hp-3784a anritsu digital transmission analyzer:me520b anritsu stm/sonet analyzer:mp1560a the following table lists the filter characteristics defined by specification: jitter tolerance test the jitter tolerance test is performed by inserting various jitter levels at selected frequencies into the 2.048 mbit/s line input of the qe1m, as shown in the table below and figure 21. data is looped back at the sdh/sonet interface and dropped by the same qe1m device. the measured value is the maximum input jit- ter that the qe1m can tolerate at its input without generating bit errors in the loopback path. figure 22 is a plot of the measured data listed in the table. specifications filter characteristics g.703 interface f1 (high pass) f3 (high pass) f4 (low pass) 2048 kbit/s 20 hz 20 db/decade 18 khz 20 db/decade 100 khz -20 db/decade filter used hp1 hp2 lp input jitter frequency requirement maximum input jitter tolerated (ui-pp) 10 hz >1.5 ui 10 ui 2.4 khz > 1.5 ui 2.3 ui 18 khz > 0.2 ui 2.2 ui 100 khz > 0.2 ui 1.0 ui
qe1m txc-04252 - 76 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 21. jitter tolerance and jitter test arrangements figure 22. jitter tolerance measurements receiver transmitter pdh digital transmission analyzer 2.048 mbit/s e1 interface qe1m te s t f i x t u r e external loopback 155 mbit/s 0.1 1 10 ui 10 100 1000 10000 100000 input jitter fre q uenc y , hz measured re q uired jitter tolerance (min)
qe1m txc-04252 - 77 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. jitter transfer test a fixed jitter level of 0.5 ui is inserted into the transmitted e1 signal. the jitter value measured is achieved using the hp1/lp filter in the pdh receiver. the jitter transfer measurements are provided in the following table and figure 23. figure 23. jitter transfer measurements input jitter filter used jitter transfer (ui - pp, max) frequency unit interval 10 hz 1.0 ui f1-f4 (hp1/lp) 0.172 ui 50 hz 1.0 ui 0.127 ui 100 hz 1.0 ui 0.117 ui 200 hz 1.0 ui 0.099 ui 600 hz 1.0 ui 0.076 ui 1000 hz 1.0 ui 0.075 ui 0.0 0.1 1.0 10.0 10 100 1000 in p ut jitter fre q uenc y ui in p ut measured
qe1m txc-04252 - 78 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. mapping jitter measurement the following table lists the mapping jitter measurements, which are made with a sdh/sonet analyzer replacing the 155 mbit/s loopback in figure 21. note 1: these values are for further study. combined jitter measurement the following table lists the combined jitter measurements. note 1: these values are written into the desynchronizer pointer leak rate register for mapper port n (register address 049, 079, 0a9, 0d9 hex, for n = 1 - 4). note 2: the limit corresponds to the pointer sequences shown in figure 24 for standard pointer test sequences, (t1 10 s, t2 > 0.75 s, t3 = 30 ms). the t3 value was constrained by test equipment limitations. g.703 interface filter characteristics maximum output jitter (ui-pp) requirement measured value 2048 kbit/s f1-f4 (hp1/lp) (note 1) 0.032 f3-f4 (hp2/lp) < 0.075 ui 0.024 pointer test sequence filter leak rate (hex) (note 1) maximum output jitter (ui - pp) requirement measured 1 single pointers of opposite polarity f1-f4 (hp1/lp) 01h 0.4 (note 2) 0.019 2 regular pointers plus one double pointer 12h 0.169 3 regular pointers with one missing pointer 12h 0.169 4 double pointers of opposite polarity 16h 0.164 1 single pointers of opposite polarity f3-f4 (hp2/lp) 01h 0.075 (note 2) 0.009 2 regular pointers plus one double pointer 12h 0.009 3 regular pointers with one missing pointer 12h 0.009 4 double pointers of opposite polarity 16h 0.009
qe1m txc-04252 - 79 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 24. standard pointer test sequences t1 t2 t3 t2 t1 t3 t3 double pointers of opposite polarity regular pointers with one missi ng value regular pointers plus one double poiner single pointers of opposite polarity (ref: itu-t g.783, fig. 6-2)
qe1m txc-04252 - 80 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. internal spot processor the internal spot processor of the qe1m device is a s onet p rocessor for o verhead t ermination. the pur- pose of the spot processor is to relieve the device ? s internal logic of the need to support relatively slow func- tions like performance monitoring and alarm handling. the utility of this feature will grow as communications standards require tighter control of data flow and network management. in addition, as boards become more densely populated with vlsi components, the availability of the spot processor will help by reducing the requirement for external components and the workload of the main processor (and the software engineers who program it). the spot processor is a programmable core which adheres to reduced instruction set computer (risc) principles. it executes one instruction per clock cycle. instructions are simple, performing data movement, basic arithmetic functions (8-bit integer operations, but no multiply/divide) and program control. the executable device microcode required for operation of the spot processor and associated descriptive text is available via the qe1m selection option of the product finder on the home page of the transwitch internet world wide web site at www.transwitch.com, where the files are provided in zip format. the spot processor is designed to run at 29.16 mhz. this clock is internally derived from the 58.32 mhz desynchronizer clock input (extck). the instruction ram (i-ram) has 2048 words of 16 bits while the data ram (d-ram) has 2048 words of 8 bits. the spot processor has access to the microprocessor interface and the add/drop engines of the qe1m via an 8-bit data bus, as shown in figure 25. the spot processor is event-driven, with each client independently and asynchronously requesting service. these maskable requests are surveyed by a task queue and prioritized by function (add, drop, line). when idle, the spot pro- cessor polls the task queue to identify the next client to be serviced. this results in a call to the appropriate subroutine(s). during each subroutine, the spot processor may transfer data to/from the add/drop engines or the microprocessor interface. the spot processor will make decisions regarding control/status and update any necessary counters and other data ram locations. the subroutine is terminated by returning to the idle loop, and the cycle is then repeated. the e1 data paths (i.e., for the add/drop engines) are implemented in free-running hardware, and are there- fore not dependent on the spot processor. the data ram contains important information about the status of the e1 channels. performance counters, j2 messages, etc., are all stored there. the external microprocessor is granted access to the internal data ram when addressing the appropriate locations. since ram access is arbitrated, the grant will not be immediate, and the rdy/dtack signal is de-asserted until the requested data becomes available. since the spot processor is effectively a very large state machine, it could enter an unforeseen state (e.g., due to a software bug or ram corruption) which prevents it from servicing all requests in a timely manner. although the data path is not interrupted, the path overhead bytes may not be correctly processed under these conditions. two status bits have been provided to detect critical errors which are indications of this status: parity error (perr) in bit 4 of addresses 028h and 029h indicates that a parity error has occurred in reading the instruction ram. watchdog timer expired (wdtexp) in bit 6 of addresses 028h and 029h indicates that the spot processor may be unable to service all requests in a timely manner. some possible causes for this condition are excessive microprocessor accesses, a spot processor clock that is running too slowly, or a software bug.
qe1m txc-04252 - 81 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. upon power-up or hardware reset, the contents of the instruction ram are assumed to be invalid and execu- tion of the spot program is internally disabled. before the spot processor can begin processing, the micro- processor must reprogram the instruction ram, using the instructions described in the following table, by performing the procedure described in the flowchart in figure 26. the 11-bit spot pc load register spotpcld at address 007h bits 2-0 and address 006h bits 7-0 is first ini- tialized. this is an offset address into the instruction ram. it may not be necessary always to write/read the entire program, but for normal operation this register should be set to 000h. in order to access the instruction ram, set to 1 the reprogram spot control bit rpspot at bit 7 in address 007h. at this time the data ram is off-line (i.e., it is inaccessible to the microprocessor), but all register-based locations are still available. spot program execution is disabled when rpspot is a 1. function "wrpc" causes the instruction ram word pointer to be loaded from the spot pc load register. the spot processor automatically increments the instruction ram word pointer, which allows the microprocessor to write all instructions to one address (100h). since the length of the instruction ram is 2048 16-bit words, 4096 iram 8-bit write functions ("iramwr") are required to program the spot processor completely. tran- switch provides the 4096 bytes of code that will implement the features mentioned in this document. it is recommended, but not required, that the writes to the instruction ram should be verified as part of the ini- tialization procedure. as shown in the flowchart, it is necessary only to use the instruction "wrpc" to reload the i-ram word pointer and then perform 4096 i-ram read cycles using the same fixed data location (100h) as that used for write (function "iramrd"). the programming procedure is completed by setting control bit rpspot to 0. at this point, the word pointer is reloaded and execution of the spot processor program execution is enabled. it is important to set control bit initsp at address 015h, bit 0 to 1 at some time after programming the spot processor. this will cause the spot processor to execute an initialization subroutine from the instruction ram that will initialize the data ram and reset its general purpose registers to allow other subroutines to begin running from a known state. table 1: reprogram functions (valid only when control bit rpspot at bit 7 in address 007h is a 1) function direction microprocessor interface address description wrpc write 102h iramptr <== spotpcld(10-0) rdpc0 read 102h read iramptr[7:0] rdpc1 read 103h read iramptr[10:8] iramwr write 100h *iramptr++ <== data iramrd read 100h data <== *iramptr++
qe1m txc-04252 - 82 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 25. schematic diagram of qe1m showing spot processor interfaces drop[a] drop[b] rx port drop engine add engine add[a] add[b] tx port p interface control/status ram i/f arbiter spot p input/output ram ram inst. data sdh/sonet line side side
qe1m txc-04252 - 83 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 26. recommended implementation flowchart for reprogramming the spot processor initialize laten = 0 hdwie = 1 sptmsk = 1 spotpcld=000h wrpc rpspot = 1 102h = 00h no more data? write next byte 100h = data no more data? read next byte data = 100h wrpc 102h = 00h wrap up rpspot = 0 download ver if y y y n n note: restsp must be 0 during reprogramming.
qe1m txc-04252 - 84 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. boundary scan introduction the boundary scan interface block provides a five-lead test access port (tap) that conforms to the ieee 1149.1 standard. this standard provides external boundary scan functions to read and write the external input/output leads from the tap for board and component test. the ieee 1149.1 standard defines the requirements of a boundary scan architecture that has been specified by the ieee joint test action group (jtag). boundary scan is a specialized scan architecture that provides observability and controllability for the interface leads of the device. as shown in figure 27, one cell of a boundary scan register is assigned to each input or output lead to be observed or tested (bidirectional leads may have two cells). the boundary scan capability is based on a test access port (tap) controller, instruction and bypass registers, and a boundary scan register bordering the input and output leads. the boundary scan test bus interface consists of four input signals (test clock (tck), test mode select (tms), test data input (tdi) and test reset (trs )) and a test data output (tdo) output signal. boundary scan signal timing is shown in 17. the tap controller receives external control information via a test clock (tck) signal and a test mode select (tms) signal, and sends control signals to the internal scan paths. detailed information on the operation of this state machine can be found in the ieee 1149.1 standard. the serial scan path architecture consists of an instruction register, a boundary scan register and a bypass register. these three serial registers are connected in parallel between the test data input (tdi) and test data output (tdo) signals, as shown in figure 27. the boundary scan function can be reset and disabled by holding lead trs low. when boundary scan testing is not being performed the boundary scan register is transparent, allowing the input and output signals to pass to and from the qe1m device ? s internal logic. during boundary scan testing, the boundary scan register may disable the normal flow of input and output signals to allow the device to be controlled and observed via scan operations. boundary scan operation the maximum frequency the qe1m device will support for boundary scan is 10 mhz. the timing diagrams for the boundary scan interface leads are shown in 17. the instruction register contains three bits. the qe1m device performs the following three boundary scan test instructions: the extest test instruction (000) provides the ability to test the connectivity of the qe1m device to external circuitry. the sample test instruction (010) provides the ability to examine the boundary scan register contents without interfering with device operation. the bypass test instruction (111) provides the ability to bypass the qe1m boundary scan and instruction registers. boundary scan reset specific control of the trs lead is required in order to ensure that the boundary scan logic does not interfere with normal device operation. this lead must either be held low, asserted low, or asserted low then high (pulsed low), to asynchronously reset the test access port (tap) controller during power-up of the qe1m. if boundary scan testing is to be performed and the lead is held low, then a pull-down resistor value should be chosen which will allow the tester to drive this lead high, but still meet the v il requirements listed in the ? input, output and input/output parameters ? section of this data sheet for worst case leakage currents of all devices sharing this pull-down resistor.
qe1m txc-04252 - 85 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. figure 27. boundary scan schematic tap controller bypass register instruction register tdi tdo in out controls boundary scan serial test data core logic of qe1m boundary scan register signal input and output leads 3 device (shown for pqfp; pbga package has solder ball leads on bottom surface).
qe1m txc-04252 - 86 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. boundary scan chain there are 159 scan cells in the boundary scan chain associated with qe1m core logic functions. bidirectional signals require two scan cells. additional scan cells are used for direction control as needed. a boundary scan description language (bsdl) source file is available via the products page of the transwitch internet world wide web site at www.transwitch.com. the following table shows the listed order of the scan cells and their function. scan cell no. i/o lead no. symbol comments pqfp pbga output 37 p1 tdo scan chain output 0 input 33 m3 adspe 1 input 32 l2 adc1j1v1 2 input 31 l1 aaspe 3 input 30 l4 aac1j1v1 4 input 28 k2 aaclk 5 input 26 k3 adclk 6 output (2-state) 24 j2 adind 7 output (2-state) 23 j3 aaind 8 input 21 h1 tpi1 9 input 20 g4 tni1 10 input 19 g1 tci1 11 input 18 g2 quiet1 12 output (3-state) 16 f4 rpo1 13 output (3-state) 15 f3 rno1 14 --- --- rn1_oe when high, lead 15 or f3 is tristated. 15 output (3-state) 14 f1 rco1 16 --- --- rcp1_oe when high, leads 14 or f1 and 16 or f4 are tristated. 17 output (3-state) 12 e4 rpo3 18 output (3-state) 11 e3 rno3 19 --- --- rn3_oe when high, lead 11 or e3 is tristated. 20 output (3-state) 10 e1 rco3 21 --- --- rcp3_oe when high, leads 10 or e1 and 12 or e4 are tristated. 22 input 8 d4 tpi3 23 input 7 d1 tni3
qe1m txc-04252 - 87 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 24 input 6 d3 tci3 25 input 5 d2 quiet3 26 input 3 c1 mux 27 input 2 b1 moto 28 input 1 c3 upa10 (a10) (in) 29 output (3-state) 1 c3 upa10 (a10) (out) although they are normally inputs, all address leads can be driven internally by the spot processor in test mode. 30 input 160 b2 upa9 (a9) (in) 31 output (3-state) 160 b2 upa9 (a9) (out) 32 input 159 a2 upa8 (a8) (in) 33 output (3-state) 159 a2 upa8 (a8) (out) 34 input 158 a3 a7 (in) 35 output (3-state) 158 a3 a7 (out) 36 input 157 a4 abust 37 --- --- upa_oe2 when high, leads 158 or a3, 159 or a2, 160 or b2 and 1 or c3 are tristated. 38 input 156 b5 a6 (in) 39 output (3-state) 156 b5 a6 (out) 40 input 155 c5 reset 41 input 153 c6 a5 (in) 42 output (3-state) 153 c6 a5 (out) 43 output (3-state) 152 d6 int/irq 44 --- --- int_oe when high, lead 152 or d6 is tristated. 45 input 150 b7 intsh 46 input 149 a7 ale used only in mux mode. 47 input 148 c7 wr (wr /lds ) 48 input 147 d7 rd (rd / rd/wr ) scan cell no. i/o lead no. symbol comments pqfp pbga
qe1m txc-04252 - 88 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 49 --- --- upa_oe1 when high, leads 144 or c8, 153 or c6 and 156 or b5 are tristated. 50 input 146 b8 sel 51 --- --- upa_oe0 when high, leads 135 or b10, 140 or b9, 141 or c9 and 143 or d8 are tristated. 52 input 145 a8 test 53 --- --- upd_oe3 when high, leads 132 or c11 and 133 or d11 are tristated. 54 input 144 c8 a4 (in) 55 output (3-state) 144 c8 a4 (out) 56 input 143 d8 a3 (in) 57 output (3-state) 143 d8 a3 (out) 58 input 141 c9 a2 (in) 59 output (3-state) 141 c9 a2 (out) 60 input 140 b9 a1 (in) 61 output (3-state) 140 b9 a1 (out) 62 input 138 d10 extck 63 --- --- upd_oe2 when high, leads 129 or a12 and 130 or c12 are tristated. 64 input 136 a10 highz 65 --- --- upd_oe1 when high, leads 126 or a13 and 128 or b12 are tristated. 66 input 135 b10 a0 (in) 67 output (3-state) 135 b10 a0 (out) 68 input 133 d11 upad7 (d7) (in) 69 output (3-state) 133 d11 upad7 (d7) (out) 70 input 132 c11 upad6 (d6) (in) 71 output (3-state) 132 c11 upad6 (d6) (out) 72 input 130 c12 upad5 (d5) (in) scan cell no. i/o lead no. symbol comments pqfp pbga
qe1m txc-04252 - 89 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 73 output (3-state) 130 c12 upad5 (d5) (out) 74 input 129 a12 upad4 (d4) (in) 75 output (3-state) 129 a12 upad4 (d4) (out) 76 input 128 b12 upad3 (d3) (in) 77 output (3-state) 128 b12 upad3 (d3) (out) 78 input 126 a13 upad2 (d2) (in) 79 output (3-state) 126 a13 upad2 (d2) (out) 80 input 125 c13 upad1 (d1) (in) 81 output (3-state) 125 c13 upad1 (d1) (out) 82 input 124 b13 upad0 (d0) (in) 83 output (3-state) 124 b13 upad0 (d0) (out) 84 output (3-state) 122 a15 rdy/dtack 85 --- --- rdy_oe when high, lead 122 or a15 is tristated. 86 input 121 c14 spare2 87 --- --- upd_oe0 when high, leads 124 or b13 and 125 or c13 are tristated. 88 input 119 b15 quiet4 89 input 118 a16 tci4 90 input 117 c15 tni4 91 input 116 c16 tpi4 92 output (3-state) 114 d14 rco4 93 output (3-state) 113 e15 rno4 94 --- --- rn4_oe when high, lead 113 or e15 is tristated. 95 output (3-state) 112 e14 rpo4 scan cell no. i/o lead no. symbol comments pqfp pbga
qe1m txc-04252 - 90 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 96 --- --- rcp4_oe when high, leads 112 or e14 and 114 or d14 are tristated. 97 output (3-state) 111 e13 rco2 98 output (3-state) 110 f16 rno2 99 --- --- rn2_oe when high, lead 110 or f16 is tristated. 100 output (3-state) 109 f14 rpo2 101 --- --- rcp2_oe when high, leads 109 or f14 and 111 or e13 are tristated. 102 input 107 g16 quiet2 103 input 106 g14 tci2 104 input 105 g13 tni2 105 input 104 h15 tpi2 106 output (2-state) 102 j13 baind 107 output (2-state) 101 j14 bdind 108 input 99 k14 bdclk 109 input 98 k16 baclk 110 input 96 l13 bac1j1v1 111 input 95 l14 baspe 112 input 94 l16 bdc1j1v1 113 input 93 l15 bdspe 114 input 91 m14 bdpar 115 input 90 m16 bd7 116 input 89 m15 bd6 117 input 88 n13 bd5 118 input 87 n16 bd4 119 input 85 p16 bd3 120 input 84 p15 bd2 121 input 83 r16 bd1 122 input 82 p14 bd0 123 input 80 r15 spare1 124 output (2-state) 78 r14 badd 125 output (3-state) 77 t14 bapar scan cell no. i/o lead no. symbol comments pqfp pbga
qe1m txc-04252 - 91 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 126 output (3-state) 76 t13 ba7 127 --- --- ba_oe2 when high, leads 75 or r13, 76 or t13 and 77 or t14 are tristated. 128 output (3-state) 75 r13 ba6 129 output (3-state) 73 r12 ba5 130 output (3-state) 72 t12 ba4 131 --- --- ba_oe1 when high, leads 71 or p12, 72 or t12 and 73 or r12 are tristated. 132 output (3-state) 71 p12 ba3 133 output (3-state) 69 t11 ba2 134 output (3-state) 68 p11 ba1 135 --- --- ba_oe0 when high, leads 67 or n11, 68 or p11 and 69 or t11 are tristated. 136 output (3-state) 67 n11 ba0 137 output (3-state) 65 t10 aa0 138 output (3-state) 64 p10 aa1 139 --- --- aa_oe0 when high, leads 63 or n10, 64 or p10 and 65 or t10 are tristated. 140 output (3-state) 63 n10 aa2 141 output (3-state) 62 r9 aa3 142 output (3-state) 60 n9 aa4 143 --- --- aa_oe1 when high, leads 59 or n8, 60 or n9 and 62 or r9 are tristated. 144 output (3-state) 59 n8 aa5 145 output (3-state) 58 p8 aa6 146 output (3-state) 56 p7 aa7 147 output (3-state) 55 t7 aapar 148 --- --- aa_oe2 when high, leads 55 or t7, 56 or p7 and 58 or p8 tristated. 149 output (2-state) 54 r7 aadd 150 input 52 n6 ad0 151 input 51 p6 ad1 152 input 50 t6 ad2 scan cell no. i/o lead no. symbol comments pqfp pbga
qe1m txc-04252 - 92 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 153 input 48 n5 ad3 154 input 47 p5 ad4 155 input 46 t5 ad5 156 input 44 p4 ad6 157 input 43 r4 ad7 158 input 42 t3 adpar input 38 r1 tdi scan chain input scan cell no. i/o lead no. symbol comments pqfp pbga
qe1m txc-04252 - 93 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. multiplex format and mapping information sts-1 vt2 (2.048 mbit/s) multiplex format mapping the following diagram and table illustrate the mapping of the 21 vt2s into an sts-1 spe. column 1 is assigned to carry the path overhead bytes. 1 2 3 36 123 5 vt vt 4 columns 1 30 2 # 21 2 # vt vt vt 2 # 2 # 2 # 23 45 vt2 j1 b3 c2 g1 f2 h4 z3 z4 4 36 2 1 vt 2 # 1 vt 2 # 2211 vt 2 # 67 59 vt 2 # 2211 21 vt 2 # 87 2 z5 vt 2 # 121 r r r r r r r r r r r r r r r r r r
qe1m txc-04252 - 94 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. sts-1 mapping (2.048 mbit/s) vt# rtunn, ttunn locations 04ch, 04dh port 1 0ach, 0adh port 3 07ch, 07dh port 2 0dch, 0ddh port 4 vt2 column numbers* 6543210 0000000 no vt selected 1 0000101 2, 23, 45, 67 2 0001001 3, 24, 46, 68 3 0001101 4, 25, 47, 69 4 0010001 5, 26, 48, 70 5 0010101 6, 27, 49, 71 6 0011001 7, 28, 50, 72 7 0011101 8, 29, 51, 73 8 0000110 9, 31, 52, 74 9 0001010 10, 32, 53, 75 10 0001110 11, 33, 54, 76 11 0010010 12, 34, 55, 77 12 0010110 13, 35, 56, 78 13 0011010 14, 36, 57, 79 14 0011110 15, 37, 58, 80 15 0000111 16, 38, 60, 81 16 0001011 17, 39, 61, 82 17 0001111 18, 40, 62, 83 18 0010011 19, 41, 63, 84 19 0010111 20, 42, 64, 85 20 0011011 21, 43, 65, 86 21 0011111 22, 44, 66, 87 * note: columns 30 and 59 carry fixed stuff bytes. column 1 is assigned for the poh bytes.
qe1m txc-04252 - 95 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. sts-3/au-3 vt2/tu-12 (2.048 mbit/s) multiplex format mapping the following diagram and table illustrate the mapping of the 63 vt2/tu-12s into an sts-3/au-3 spe. each sts-3 carries three sts-1s. column 1 in each sts-1/au-3 is assigned to carry the path overhead bytes. sts-3/au-3 spe 1 2 3 36 12 3 5 35 vt vt vt vt 1 261 4 columns 14459 871 87 j1 b3 c2 g1 f2 h4 z3 z4 z5 j1 b3 c2 g1 f2 h4 z3 z4 z5 j1 b3 c2 g1 f2 h4 z3 z4 z5 2 # 7 2 # 2 # 21 vt vt vt vt vt vt vt 2 # 2 # 2 # 2 # 2 # 2 # 2 # 42 2 # 30 29 66 1 vt2 3 r r r r r r r r r r r r r r r r r r 23 vt 2 # 87 vt 2 # 63 36 4 43 22 23 1 21 60 vt 2 # 15 1 21 11 45 67 36 bytes vt 2 # 44 vt 2 # note: columns 88, 89, 90, 175, 176 and 177 are fixed stuff.
qe1m txc-04252 - 96 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. sts-3/au-3 mapping (2.048 mbit/s) * note: columns 88, 89, 90, 175, 176 and 177 are fixed stuff. tu/ vt # rtunn, ttunn 04ch, 04dh port 1 07ch, 07dh port 2 0ach, 0adh port 3 0dch, 0ddh port 4 registers 6 5 4 3 2 1 0 sts-3/au-3 column numbers* tu/ vt # rtunn, ttunn 04ch, 04dh port 1 07ch, 07dh port 2 0ach, 0adh port 3 0dch, 0ddh port 4 registers 6 5 4 3 2 1 0 sts-3/au-3 column numbers* tu/ vt # rtunn, ttunn 04ch, 04dh port 1 07ch, 07dh port 2 0ach, 0adh port 3 0dch, 0ddh port 4 registers 6 5 4 3 2 1 0 sts-3/au-3 column numbers* 0 0 0 0 0 0 0 no tu/vt selected 1 0 1 0 0 1 0 1 4, 67, 133, 199 22 1 0 0 0 1 0 1 5, 68, 134, 200 43 1 1 0 0 1 0 1 6, 69, 135, 201 2 0 1 0 1 0 0 1 7, 70, 136, 202 23 1 0 0 1 0 0 1 8, 71, 137, 203 44 1 1 0 1 0 0 1 9, 72, 138, 204 3 0 1 0 1 1 0 1 10, 73, 139, 205 24 1 0 0 1 1 0 1 11, 74, 140, 206 45 1 1 0 1 1 0 1 12, 75, 141, 207 4 0 1 1 0 0 0 1 13, 76, 142, 208 25 1 0 1 0 0 0 1 14, 77, 143, 209 46 1 1 1 0 0 0 1 15, 78, 144, 210 5 0 1 1 0 1 0 1 16, 79, 145, 211 26 1 0 1 0 1 0 1 17, 80, 146, 212 47 1 1 1 0 1 0 1 18, 81, 147, 213 6 0 1 1 1 0 0 1 19, 82, 148, 214 27 1 0 1 1 0 0 1 20, 83, 149, 215 48 1 1 1 1 0 0 1 21, 84, 150, 216 7 0 1 1 1 1 0 1 22, 85, 151, 217 28 1 0 1 1 1 0 1 23, 86, 152, 218 49 1 1 1 1 1 0 1 24, 87, 153, 219 8 0 1 0 0 1 1 0 25, 91, 154, 220 29 1 0 0 0 1 1 0 26, 92, 155, 221 50 1 1 0 0 1 1 0 27, 93, 156, 222 9 0 1 0 1 0 1 0 28, 94, 157, 223 30 1 0 0 1 0 1 0 29, 95, 158, 224 51 1 1 0 1 0 1 0 30, 96, 159, 225 10 0 1 0 1 1 1 0 31, 97, 160, 226 31 1 0 0 1 1 1 0 32, 98, 161, 227 52 1 1 0 1 1 1 0 33, 99, 162, 228 11 0 1 1 0 0 1 0 34, 100, 163, 229 32 1 0 1 0 0 1 0 35, 101, 164, 230 53 1 1 1 0 0 1 0 36, 102, 165, 231 12 0 1 1 0 1 1 0 37, 103, 166, 232 33 1 0 1 0 1 1 0 38, 104, 167, 233 54 1 1 1 0 1 1 0 39, 105, 168, 234 13 0 1 1 1 0 1 0 40, 106, 169, 235 34 1 0 1 1 0 1 0 41, 107, 170, 236 55 1 1 1 1 0 1 0 42, 108, 171, 237 14 0 1 1 1 1 1 0 43, 109, 172, 238 35 1 0 1 1 1 1 0 44, 110, 173, 239 56 1 1 1 1 1 1 0 45, 111, 174, 240 15 0 1 0 0 1 1 1 46, 112, 178, 241 36 1 0 0 0 1 1 1 47, 113, 179, 242 57 1 1 0 0 1 1 1 48, 114, 180, 243 16 0 1 0 1 0 1 1 49, 115, 181, 244 37 1 0 0 1 0 1 1 50, 116, 182, 245 58 1 1 0 1 0 1 1 51, 117, 183, 246 17 0 1 0 1 1 1 1 52, 118, 184, 247 38 1 0 0 1 1 1 1 53, 119, 185, 248 59 1 1 0 1 1 1 1 54, 120, 186, 249 18 0 1 1 0 0 1 1 55, 121, 187, 250 39 1 0 1 0 0 1 1 56, 122, 188, 251 60 1 1 1 0 0 1 1 57, 123, 189, 252 19 0 1 1 0 1 1 1 58, 124, 190, 253 40 1 0 1 0 1 1 1 59, 125, 191, 254 61 1 1 1 0 1 1 1 60, 126, 192, 255 20 0 1 1 1 0 1 1 61, 127, 193, 256 41 1 0 1 1 0 1 1 62, 128, 194, 257 62 1 1 1 1 0 1 1 63, 129, 195, 258 21 0 1 1 1 1 1 1 64, 130, 196, 259 42 1 0 1 1 1 1 1 65, 131, 197, 260 63 1 1 1 1 1 1 1 66, 132, 198, 261 sts-1 #1, au-3 a sts-1 #2, au-3 b sts-1 #3, au-3 c
qe1m txc-04252 - 97 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. stm-1/vc-4 tu-12 (2048 kbit/s) multiplex format mapping the following diagram and table illustrate the mapping of the 63 tu-12s into an stm-1/vc-4. the qe1m pro- vides control bits for enabling the null pointer indicators (npis) for the columns indicated. 1 2 3 36 123 5 2 3 1 3 1 2 1 2 3 77717 n p i n p i 14 n p i 15 p o h 1 261 4 columns tu-12 #1 tug-2 #1 16686186 vc-4 86 3 1 2 1 21 8 1 4 36 1 45 1 324 tug-3a tug-3b tug-3c stm-1/vc-4
qe1m txc-04252 - 98 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. stm-1 vc-4 mode (2048 kbit/s) tu # rtunn, ttunn 04ch, 04dh port 1 07ch, 07dh port 2 0ach, 0adh port 3 0dch, 0ddh port 4 registers 6 5 4 3 2 1 0 vc-4 column numbers tu # rtunn, ttunn 04ch, 04dh port 1 07ch, 07dh port 2 0ach, 0adh port 3 0dch, 0ddh port 4 registers 6 5 4 3 2 1 0 vc-4 column numbers tu # rtunn, ttunn 04ch, 04dh port 1 07ch, 07dh port 2 0ach, 0adh port 3 0dch, 0ddh port 4 registers 6 5 4 3 2 1 0 vc-4 column numbers 0 0 0 0 0 0 0 no tu selected 1 0 1 0 0 1 0 1 10, 73, 136, 199 22 1 0 0 0 1 0 1 11, 74, 137, 200 43 1 1 0 0 1 0 1 12, 75, 138, 201 2 0 1 0 1 0 0 1 13, 76, 139, 202 23 1 0 0 1 0 0 1 14, 77, 140, 203 44 1 1 0 1 0 0 1 15, 78, 141, 204 3 0 1 0 1 1 0 1 16, 79, 142, 205 24 1 0 0 1 1 0 1 17, 80, 143, 206 45 1 1 0 1 1 0 1 18, 81, 144, 207 4 0 1 1 0 0 0 1 19, 82, 145, 208 25 1 0 1 0 0 0 1 20, 83, 146, 209 46 1 1 1 0 0 0 1 21, 84, 147, 210 5 0 1 1 0 1 0 1 22, 85, 148, 211 26 1 0 1 0 1 0 1 23, 86, 149, 212 47 1 1 1 0 1 0 1 24, 87, 150, 213 6 0 1 1 1 0 0 1 25, 88, 151, 214 27 1 0 1 1 0 0 1 26, 89, 152, 215 48 1 1 1 1 0 0 1 27, 90, 153, 216 7 0 1 1 1 1 0 1 28, 91, 154, 217 28 1 0 1 1 1 0 1 29, 92, 155, 218 49 1 1 1 1 1 0 1 30, 93, 156, 219 8 0 1 0 0 1 1 0 31, 94, 157, 220 29 1 0 0 0 1 1 0 32, 95, 158, 221 50 1 1 0 0 1 1 0 33, 96, 159, 222 9 0 1 0 1 0 1 0 34, 97, 160, 223 30 1 0 0 1 0 1 0 35, 98, 161, 224 51 1 1 0 1 0 1 0 36, 99, 162, 225 10 0 1 0 1 1 1 0 37, 100, 163, 226 31 1 0 0 1 1 1 0 38, 101, 164, 227 52 1 1 0 1 1 1 0 39, 102, 165, 228 11 0 1 1 0 0 1 0 40, 103, 166, 229 32 1 0 1 0 0 1 0 41, 104, 167, 230 53 1 1 1 0 0 1 0 42, 105, 168, 231 12 0 1 1 0 1 1 0 43, 106, 169, 232 33 1 0 1 0 1 1 0 44, 107, 170, 233 54 1 1 1 0 1 1 0 45, 108, 171, 234 13 0 1 1 1 0 1 0 46, 109, 172, 235 34 1 0 1 1 0 1 0 47, 110, 173, 236 55 1 1 1 1 0 1 0 48, 111, 174, 237 14 0 1 1 1 1 1 0 49, 112, 175, 238 35 1 0 1 1 1 1 0 50, 113, 176, 239 56 1 1 1 1 1 1 0 51, 114, 177, 240 15 0 1 0 0 1 1 1 52, 115, 178, 241 36 1 0 0 0 1 1 1 53, 116, 179, 242 57 1 1 0 0 1 1 1 54, 117, 180, 243 16 0 1 0 1 0 1 1 55, 118, 181, 244 37 1 0 0 1 0 1 1 56, 119, 182, 245 58 1 1 0 1 0 1 1 57, 120, 183, 246 17 0 1 0 1 1 1 1 58, 121, 184, 247 38 1 0 0 1 1 1 1 59, 122, 185, 248 59 1 1 0 1 1 1 1 60, 123, 186, 249 18 0 1 1 0 0 1 1 61, 124, 187, 250 39 1 0 1 0 0 1 1 62, 125, 188, 251 60 1 1 1 0 0 1 1 63, 126, 189, 252 19 0 1 1 0 1 1 1 64, 127, 190, 253 40 1 0 1 0 1 1 1 65, 128, 191, 254 61 1 1 1 0 1 1 1 66, 129, 192, 255 20 0 1 1 1 0 1 1 67, 130, 193, 256 41 1 0 1 1 0 1 1 68, 131, 194, 257 62 1 1 1 1 0 1 1 69, 132, 195, 258 21 0 1 1 1 1 1 1 70, 133, 196, 259 42 1 0 1 1 1 1 1 71, 134, 197, 260 63 1 1 1 1 1 1 1 72, 135, 198, 261
qe1m txc-04252 - 99 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. memory map the qe1m memory map consists of counters and register bit positions which may be accessed by the micro- processor. the memory map segment consists of 7ff (hex) address locations. address locations in the range 000h - 7ffh that are shown as unused, or are unlisted, must not be accessed by the microprocessor. unused bit positions within register locations will contain unspecified values when read, unless a 0 or 1 value is indi- cated in the tables below, or the address can be written by the microprocessor, in which case unused bit posi- tions must always be set to 0. all counters saturate at full count and are cleared when they are read. the common memory map segment consists of the device id, program id, internal processor, control, provi- sioning, interrupt indication, and interrupt status registers. the a bus segment consists of the a drop and add status registers. the b bus segment consists of the b drop and add status registers. each port n memory map segment (where n = 1-4) consists of the desynchronizer, provisioning, status and operations registers, and various counters. there are also port n registers for j2 and n2 (z6) message segments. some memory locations, at addresses 032h and above, are shown shaded in the memory map. these loca- tions reside in the 2k x 8 data ram of the internal spot processor and are not reset by the software or hard- ware resets but only by initsp. they are subject to arbitrated access by both the internal spot processor and the external microprocessor. an attempt to access any of these locations will toggle the rdy/dtack out- put lead to pause the external microprocessor until the location is available for external access. while control bit rpspot is set to 1, these locations are assigned to use by the spot processor and must not be accessed by the external microprocessor unless they are addresses designated for microprocessor access while the spot processor is being reprogrammed (i.e., addresses 100h, 102h and 103h). device id program id * r=read only; r(l)=read only (latched); r/w=read/write; w=write only. address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000r11010111 001r11000000 002r00001001 003 r revision (version) level 0 0 0 1 004 r mask level (reads as 0000) growth (reads as 0000) address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 6bd r/w program revision checksum/execution flag (pid-chk) 6be r/w part 1 of two-part program release number (pgmrv1) 6bf r/w part 2 of two-part program release number (pgmrv2)
qe1m txc-04252 - 100 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. internal processor (spot) common registers - controls common registers - provisioning (control) common registers - interrupt indication common registers - interrupt mask * r=read only; r(l)=read only (latched); r/w=read/write; w=write only. address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 005 r/w transwitch test register (set to 00h) 006 r/w spotpcld (7 - 0) 007 r/w rpspot transwitch test bits (set to 0000) spotpcld (10 - 8) 008 r/w transwitch test register (set to 00h) address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 010 r/w mod1 mod0 aahze bahze block npia npib npic 011 r/w sbten drpbt abd laten taise tclki raise rclki 012 r/w addi ape ipos ineg rfie thrsby dpe pddo 013 r/w heaise dv1sel dv1ref rdien nullz ddind uqae tobwz address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 014 r/w unused (set to 000) ueame se1ais v5al10 ptalte hdwie 015 w reset restab restbb restsp unused (set to 000) initsp 0f1r/w0000v4en000 0f5r/wtxb2dis0000000 address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 020 r int extck aside bside port4 port3 port2 port1 address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 016r/w0000000sptmsk 017 r/w rpt4a rpt4b rpt3a rpt3b rpt2a rpt2b rpt1a rpt1b 018 r/w tfifo4a tfifo4b tfifo3a tfifo3b tfifo2a tfifo2b tfifo1a tfifo1b 019 r/w tport4 tport3 tport2 tport1 rfifo4 rfifo3 rfifo2 rfifo1 021 r/w 0 eckmsk asmsk bsmsk p4msk p3msk p2msk p1msk
qe1m txc-04252 - 101 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. a/b drop and add bus registers - desynchronizer and internal processor (spot) status desynchronizer control - port n provisioning (control) - port n * r=read only; r(l)=read only (latched); r/w=read/write; w=write only. address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 022 r(l) adloc aaloc adpar 0 0 a3uaisi a2uaisi a1uaisi 023 r adloc aaloc adpar 0 0 a3uaisi a2uaisi a1uaisi 024 r(l) lextc 0 0 0 0 a3dh4e a2dh4e a1dh4e 025 r lextc 0 0 0 0 a3dh4e a2dh4e a1dh4e 026 r(l) bdloc baloc bdpar 0 0 b3uaisi b2uaisi b1uaisi 027 r bdloc baloc bdpar 0 0 b3uaisi b2uaisi b1uaisi 028 r(l) sptloc wdtexp 0 perr 0 b3dh4e b2dh4e b1dh4e 029 r sptloc wdtexp 0 perr 0 b3dh4e b2dh4e b1dh4e address port 1, 2, 3, 4 status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 049 079 0a9 0d9 r/w desynchronizer pointer leak rate register address port 1, 2, 3, 4 status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 04a 07a 0aa 0da r/w tnsel1 tnsel0 rnsel uchne uschne bypasn rnen 0 04b 07b 0ab 0db r/w adnen bdnen aanen banen anantx ananen prbsnen frdisn 04c 07c 0ac 0dc r/w 0 receive tu/vt select (rtunn) 04d 07d 0ad 0dd r/w 0 transmit tu/vt select (ttunn)
qe1m txc-04252 - 102 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. status registers and counters - port n (a side) * r=read only; r(l)=read only (latched); r/w=read/write; w=write only. address port 1, 2, 3, 4 status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 030 060 090 0c0 r(l) anais anlop ansize anndf anrdis anrfi anuneq ansler 031 061 091 0c1 r anais anlop ansize anndf anrdis anrfi anuneq ansler 032 062 092 0c2 r anpj counter annj counter 033 063 093 0c3 r anbip2 error counter 034 064 094 0c4 r anfebe counter 035 065 095 0c5 r unused an rx label 04e 07e 0ae 0de r(l) anrdip anrdic unused (00) anj2lol anj2tim unused (00) 04f 07f 0af 0df r anrdip anrdic unused (00) anj2lol anj2tim unused (00) 036 066 096 0c6 r unused 037 067 097 0c7 r unused 038 068 098 0c8 r an receive k4 (z7) byte 039 069 099 0c9 r an receive o-bits 05a 08a 0ba 0ea r(l) antcuq antcais antclm antcll antctm antcodi antcrdi 0 05b 08b 0bb 0eb r antcuq antcais antclm antcll antctm antcodi antcrdi 0 100 200 300 400 r an tc bip-2 error counter 101 201 301 401 r an tc rei counter 102 202 302 402 r an tc oei counter 116 216 316 416 r an receive v4 byte
qe1m txc-04252 - 103 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. status registers - port n (b side) status registers - port n (a and b sides) * r=read only; r(l)=read only (latched); r/w=read/write; w=write only. address port 1, 2, 3, 4 status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 03a 06a 09a 0ca r(l) bnais bnlop bnsize bnndf bnrdis bnrfi bnuneq bnsler 03b 06b 09b 0cb r bnais bnlop bnsize bnndf bnrdis bnrfi bnuneq bnsler 03c 06c 09c 0cc r bnpj counter bnnj counter 03d 06d 09d 0cd r bnbip2 error counter 03e 06e 09e 0ce r bnfebe counter 03f 06f 09f 0cf r unused bn rx label 05e 08e 0be 0ee r(l) bnrdip bnrdic unused (00) bnj2lol bnj2tim unused (00) 05f 08f 0bf 0ef r bnrdip bnrdic unused (00) bnj2lol bnj2tim unused (00) 040 070 0a0 0d0 runused 041 071 0a1 0d1 runused 042 072 0a2 0d2 r bn receive k4 (z7) byte 043 073 0a3 0d3 r bn receive o-bits 05c 08c 0bc 0ec r(l) bntcuq bntcais bntclm bntcll bntctm bntcodi bntcrdi 0 05d 08d 0bd 0ed r bntcuq bntcais bntclm bntcll bntctm bntcodi bntcrdi 0 180 280 380 480 r bn tc bip-2 error counter 181 281 381 481 r bn tc rei counter 182 282 382 482 r bn tc oei counter 196 296 396 496 r bn receive v4 byte address port 1, 2, 3, 4 status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 044 074 0a4 0d4 r(l) rnffe 0 ananool tanfe tbnfe tnlos tnloc tndais 045 075 0a5 0d5 r rnffe 0 ananool tanfe tbnfe tnlos tnloc tndais 046 076 0a6 0d6 r port n hdb3 coding errors (low byte) 047 077 0a7 0d7 r port n hdb3 coding errors (high byte)
qe1m txc-04252 - 104 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. operations (control) registers - port n j2 and n2 (z6) message segments - port n where x = 1 for port 1, 2 for port 2, 3 for port 3, 4 for port 4. * r=read only; r(l)=read only (latched); r/w=read/write; w=write only. address port 1, 2, 3, 4 status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 048 078 0a8 0d8 r/w unused (set to 000) 1bnrdi j2nten j2nsize j2ncom j2naise 050 080 0b0 0e0 r/w fnlbk lnlbk rnais tnais tnvtais tnrfi tnrdis tnrdip 051 081 0b1 0e1 r/w tcnrdi tcnodi tcnais tcnen tcnre tcnoe tcnaen tnrdic 052 082 0b2 0e2 w rnsets rnsetc unused (set to 0000) tnfb2 tnffb 053 083 0b3 0e3 r/w unused (set to 00000) an p mismatch label 054 084 0b4 0e4 r/w unused (set to 00000) bn p mismatch label 055 085 0b5 0e5 r/w unused (set to 00000) tn tx label 056 086 0b6 0e6 r/w unused 057 087 0b7 0e7 r/w unused 058 088 0b8 0e8 r/w transmit k4 (z7) byte value (4-7) unused (set to 000) tz7bv(0) 059 089 0b9 0e9 r/w transmit o-bits - port n 511 591 611 691 r/w transmit v4 bytes - port n address port 1, 2, 3, 4 status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 140 240 340 440 to 17f 27f 37f 47f r/w por t n a side j2 64-byte trace message received (x40 - x7f) or a side j2 16-byte trace message received (x40 - x4f) a side j2 16-byte microprocessor-written trace message (x50 - x5f) a side tc (n2 (z6)) 16-byte trace message received (x60 - x6f) a side tc (n2 (z6)) 16-byte microprocessor-written trace message (x70 - x7f) 1c0 2c0 3c0 4c0 to 1ff 2ff 3ff 4ff r/w por t n b side j2 64-byte trace message received (xc0 - xff) or b side j2 16-byte trace message received (xc0 - xcf) b side j2 16-byte microprocessor-written trace message (xd0 - xdf) b side tc (n2 (z6)) 16-byte trace message received (xe0 - xef) b side tc (n2 (z6)) 16-byte microprocessor-written trace message (xf0 - xff) 540 5c0 640 6c0 to 57f 5ff 67f 6ff r/w por t n j2 64-byte trace message transmitted (540 - 57f port 1, 5c0 - 5ff port 2, 640 - 67f port 3, 6c0 - 6ff port 4) or j2 16-byte trace message transmitted (540-54f port 1, 5c0-5cf port 2, 640-64f port 3, 6c0-6cf port 4) tc (n2 (z6)) 16-byte trace message transmitted (560-56f port 1, 5e0-5ef port 2, 660-66f port 3, 6e0-6ef port 4)
qe1m txc-04252 - 105 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. memory map descriptions common registers - program id common registers - internal processor (spot) address bit symbol description 6bd 7-0 pid-chk this value (register 6beh + register 6bfh + 0x55) is written by spot during initialization, and at the start of each maintenance cycle (2 khz rate). the external microprocessor can read this checksum to validate the revision numbers in registers 6beh and 6bfh. by writing this loca- tion with a different value, waiting at least 1 ms, and then reading this location, the external microprocessor can determine whether the spot program is running. 6be 7-0 pgmrv1* part 1 of two-part program release number. 6bf 7-0 pgmrv2* part 2 of two-part program release number. * registers 6beh and 6bfh contain the two-part spot program release number. in documentation, this number is written as ? pgmrv1, pgmrv2 ? . address bit symbol description 005 7-0 transwitch test register: these bits must be written to 0. 006 7-0 spotpcld internal spot processor load register: these bits are the lower 8 bits of the 11-bit register which is used as the offset address access for the spot instruction ram. during normal operation these bits must be written to 0. 007 7 rpspot reprogram internal spot processor control bit: this bit is written to 1 for accessing the spot instruction ram. during normal operation this bit must be written to 0. 6-3 transwitch test bits: these bits must be written to 0. 2-0 spot pc load internal spot processor load register: these bits are the upper 3 bits of the 11-bit register which is used as the offset address access for the spot instruction ram. during normal operation these bits must be written to 0. 008 7-0 transwitch test register : these bits must be written to 0.
qe1m txc-04252 - 106 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. common registers - control descriptions address bit symbol description 010 7 6 mod1 mod0 format selection: the format selection is made according to the table given below. mod1 mod0 format selected 0 0 sts-1 format 0 1 sts-3 format 10stm-1/au-3 format 1 1 stm-1/tug-3/vc-4 format 5aahze a add bus high impedance enable: a 1 forces the a-side add bus data output to a high impedance state. upon power-up, or on a hardware or software reset, this bit is set to a 1. note: for normal bus operation this bit position must be written with a 0. see note 1. 4bahze b add bus high impedance enable: a 1 forces the b-side add bus data output to a high impedance state. upon power-up, or on a hardware or software reset, this bit is set to a 1. note: for normal bus operation this bit position must be written with a 0. see note 1 3block block count: a 1 enables two bip-2 errors to be counted as a single error (block) for the bip-2 performance counters (v5 and k4 (z7) bytes). a 0 enables two bip-2 errors to be counted as two errors. 2 1 0 npia npib npic null pointer indicator selection: a 1 enables a null pointer indicator to be generated for the corresponding tug-3 when control bits mod1 and mod0 are a 1 (stm-1/tug-3/vc-4 format). a null pointer indicator is carried in the first three bytes of column 1 in a tug-3. the null pointer indicator byte values are 93h, e0h and 00h. a 0 forces the npi byte position to a high impedance state on the a/b buses. note 1: the add bus will be forced to a high impedance state automatically when loss of clock is detected on the transmit clock signal selected by control bit dbpbt.
qe1m txc-04252 - 107 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 011 7 sbten software bus timing enable : this bit works in conjunction with control bit drpbt in bit 6 and the abust lead according to the following table (where x = don ? t care): sbten drpbt abust action 0 x low add bus timing selected. add bus data derived from add bus timing signals. software control of bus timing disabled. 0 x high drop bus timing selected. add bus data derived from like-named drop bus. software control of bus timing disabled. 1 0 x add bus timing selected. add bus data derived from add bus timing signals. hardware control of bus timing dis- abled. 1 1 x drop bus timing selected. add bus data derived from like-named drop bus. hardware control of bus timing dis- abled. this sbten bit is reset to 0 upon power-up and by a device reset. 6 drpbt drop bus timing: enabled when a 1 is written to control bit sbten. a 1 selects the drop bus timing mode, while a 0 selects the add bus timing mode. see table above. 5abd add bus delay: a 0 delays the add bus data with respect to the drop bus by one clock cycle, when the drop bus or add bus timing modes are selected. a 1 delays the add bus data with respect to the drop bus or add bus by one additional clock cycle, for a total of two clock cycles. 4laten latch on transitions enable bit: a 0 disables the states of the ipos and ineg control bits, and causes the event alarm bits (latched alarm bits in the registers) to latch on the positive (1) level of an alarm. a 1 enables the states of the ipos and ineg control bits in register 012h. 3taise transmit e1 line ais enable: a common control for all four ports. a 1 enables an e1 ais (unframed all ones) to be generated and sent from port n to the sdh/sonet side when an e1 line input loss of signal, or loss of clock, occurs for port n. 2tclki transmit e1 line clock inversion: a common control for the four ports. a 0 enables transmit data to be clocked in on the negative (falling) clock edges. a 1 enables transmit data to be clocked in on the positive (rising) clock edges. address bit symbol description
qe1m txc-04252 - 108 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 011 (cont.) 1raise receive e1 line ais enable: a common control for the four ports. a 1 enables a receive e1 ais to be sent from port n when internal defined alarms occur for a port n. an e1 ais is an unframed all ones signal. for example, receive ais for port 1 will be generated: - when r1sel is 0 and any of: - loss of pointer detected (a1lop) - vt ais detected (a1ais) - a drop bus loss of clock (adloc) - a drop bus upstream ais detected (asuaisi) when heaise is 1. - or when r1sel is 0 and raise is 1 (drop vt from a side) and any of: - a drop h4 error (asdh4e) when dv1sel is 0 - unequipped signal label (a1uneq) and uqae is 1 - mismatch signal label (a1sler) - j2 loss of lock alarm (a1j2lol) when j21com and j21aise are 1, and j21size=0 - j2 mismatch alarm (a1j2tim) when j21com and j21aise are 1, and j21size=0 - tc unequipped alarm (a1tcuq) when tc1en and tc1aen are 1 - tc loss of lock alarm (a1tcll) when tc1en and tc1aen are 1 - tc mismatch alarm (a1tctm) when tc1en and tc1aen are 1 - tc loss of multiframe alarm (a1tclm) when tc1en and tc1aen are 1 - tc ais detected (a1tcais) when tc1en and tc1aen are 1. - or when r1sel is a 1 and any of: - loss of pointer detected (b1lop) - vt ais detected (b1ais) - b drop bus loss of clock (bdloc) - b drop bus upstream ais detected (bsuaisi) and heaise is 1. - or when r1sel is 1 and raise is 1 (drop vt from b side) and any of: - b drop h4 error (bsdh4e) when dv1sel is 0 - unequipped signal label (b1uneq) and uqae is 1 - mismatch signal label (b1sler) - j2 loss of lock alarm (b1j2lol) when j21com and j21aise are 1, and j21size=0. - j2 mismatch alarm (b1j2tim) when j21com and j21aise are 1, and j21size=0 - tc unequipped alarm (b1tcuq) when tc1en and tc1aen are 1 - tc loss of lock alarm (b1tcll) when tc1en and tc1aen are 1 - tc mismatch alarm (b1tctm) when tc1en and tc1aen are 1 - tc loss of multiframe alarm (b1tclm) when tc1en and tc1aen are 1 - tc ais detected (b1tcais) when tc1en and tc1aen are 1. - or when receive fifo error (r1ffe) and raise are 1. - or when a 1 is written to send receive ais (r1ais). - or when rtun1 is invalid. the ais will be sent for one multiframe when a receive fifo error occurs. the s in asuaisi, bsuaisi, asdh4e and bsdh4e represents the sts-1 or tug in which the tu/vt has been selected, where s = 1-3. 0 rclki receive e1 line clock inversion: a common control for the four ports. a 0 enables the e1 receive data signal to be clocked out on positive (ris- ing) rcon clock edges. a 1 causes e1 data to be clocked out on nega- tive (falling) rcon clock edges. address bit symbol description
qe1m txc-04252 - 109 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 012 7 addi add indicator inversion: a 1 causes the a and b add bus output indi- cator signals (aadd and badd ) to be active high instead of active low when a time slot is added to the bus. 6 ape a/b add bus even parity generated: a 1 enables even parity to be generated, while a 0 enables odd parity to be generated. parity is calcu- lated over the data byte only. 5 4 ipos ineg interrupt/event positive/negative alarm transition selection: an event register bit will latch, and a software interrupt indication will occur, according to the transitions given in the table below. the appropriate interrupt mask bit(s) must be set if an interrupt is required. a hardware interrupt occurs when the hardware interrupt bit is also enabled (control bit hdwie is 1). these bits are disabled when a 0 is written to control bit laten. ipos ineg action 0 0 no event or interrupt indication 1 0 event and interrupt on positive alarm transition 0 1 event and interrupt on negative alarm transition 1 1 event and interrupt on both positive and negative alarm transitions 3rfie rfi enable: a common control bit for all four ports. a 1 enables an rfi indication to cause an interrupt. a 0 disables an rfi indication (bit 4 in v5 of the tu/vt) from causing an interrupt. 2 thrsby threshold modulation disabled: a 1 disables the threshold modula- tion capability in each of the four modulation circuits. a 0 enables thresh- old modulation capability in each of the four modulation circuits. 1dpe a/b drop bus even parity detected: this bit works in conjunction with the pddo control bit to determine the parity calculation in the drop direc- tion. dpe pddo action (for both a and b buses) 0 0 odd parity check over drop data, spe, and c1j1v1. 0 1 odd parity check over drop data only. 1 0 even parity check over drop data, spe, and c1j1v1. 1 1 even parity check over drop data only. other than reporting the event, no action is taken upon parity error indi- cation. 0 pddo a/b drop bus parity detected on data only: common control bit for both buses. a 1 causes parity to be calculated over the data byte only. a 0 causes parity to be calculated over the data byte, spe and c1j1v1 signals. please refer to the table provided for dpe. address bit symbol description
qe1m txc-04252 - 110 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 013 7 heaise a/b h1/h2 or e1 byte ais enable: common control for both the a and b drop buses. a 1 enables an ais detected in either the sdh/sonet h1/h2 bytes, or in the e1 bytes, to generate a receive e1 line ais and transmit an rdi (when enabled). 6 dv1sel drop bus v1 reference enable: common control bit for both buses. in the drop bus timing mode this bit must be set to zero. in the add bus timing mode this control bit works in conjunction with the dv1ref con- trol bit according to the following table. 5dv1ref drop bus v1 reference enable: common control bit for both buses. enabled when add bus timing is selected. this control bit works in con- junction with the dv1sel control bit according to the following table: dv1sel dv1ref action 0 0 drop side uses h4 multiframe detector to deter- mine v1 pulse add side uses v1 pulse from add bus c1j1v1 signal 0 1 drop side uses h4 multiframe detector to deter- mine v1 pulse add side uses v1 pulse from drop side h4 multiframe detector 1 0 drop side uses v1 pulse from drop bus c1j1v1 signal add side uses v1 pulse from add side c1j1v1 signal 1 1 drop side uses v1 pulse from drop side c1j1v1 signal add side uses v1 pulse from drop side c1j1v1 signal 4rdien transmit remote defect indication enable: common control for both buses. this control bit enables incoming receive side (drop) alarms to generate a remote defect indication in the transmit (add) direction. this bit also works in conjunction with the control bit 1bnrdi found in the operations (control) registers (048h, 078h, 0a8h, 0d8h). more details of how these control bits function can be found in the oper- ation section on remote defect indications. 3 nullz force the npi column unused bytes to zero: a 1 forces to 00h the unused bytes in the column following the npi bytes when the npi fea- ture is enabled for the same tug-3 (npia, npib or npic is a 1). a 0 forces the unused bytes following the npi to a high impedance state on the a/b buses. 2 ddind delay drop bus indication signal: a 1 increases the delay of the drop bus indication signals (adind and bdind ) by one clock cycle. 1uqae unequipped alarm ais/rdi/tc alarm enable: a common control for both the a and b drop buses. a 1 enables a receive e1 line ais, an rdi and both of the tc alarms (tcnodi, tcnrdi) to be transmitted when an unequipped alarm is detected in either the a or b drop bus signals. 0tobwz transmit o-bit channel with zeros: a common control for all four ports. a 0 enables the microprocessor-written values for the o-bit chan- nel and the unused bits in the k4 (z7) byte to be transmitted. a 1 forces the o-bit channel and the unused bits in the k4 (z7) byte to be transmit- ted as zero for all four ports. address bit symbol description
qe1m txc-04252 - 111 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. common registers - provisioning descriptions address bit symbol description 014 7-5 unused unused: these bits must be written to 0. 4ueame unequipped all modes enable: a 0 enables an unequipped channel or an unequipped supervisory channel to be generated in the multiplexer mode only, according to the table given below: drop add action a b unequipped or unequipped supervisory channel can be transmitted for the tu/vt selected on the a bus. b a unequipped or unequipped supervisory channel can be transmitted for the tu/vt selected on the b bus. a 1 enables an unequipped channel or unequipped supervisory channel to be transmitted only on the active bus for the tu/vt selected. see control bits uchne and uschne below (addresses 04a, 07a, 0aa, 0da) for associated control functions. 3se1ais select e1ais: a 1 disables the toh h1/h2n ais detection circuit and enables the ais detection circuit for the toh e1n bytes. a 0 enables the ais detection circuit for the h1/h2n bytes. here the value of n is 1 for an stm-1 format and 1, 2 or 3 for an au-3/sts-1 signal. 2v5al10 v5 alarm detection select 10: a 1 selects 10 consecutive rdi asser- tions for detection and recovery. a 0 selects 5 consecutive rdi asser- tions for detection and recovery. 1ptalte pointer tracking ais to lop transition enabled: a 1 enables the ais to lop transition in the pointer tracking state machine, as required by etsi standards. a 0 will disable the transition, as required by bellcore and ansi standards. 0hdwie hardware interrupt enable: a 1 enables the interrupt lead to be acti- vated when an interrupt occurs. 015 7 reset reset: a 1 clears to zero all controls, alarms, internal counters and per- formance counters, sets control bits aahze and bahze to 1, and re-ini- tializes the receive and transmit fifos. this bit is self-clearing, and will reset to 0 after the reset cycle is completed. see note 1. 6restab reset a side bus alarms: a 1 clears the alarms associated with the a side bus and the lextc alarm. this bit is self-clearing, and will reset to 0 after the reset cycle is completed. see note 2. 5restbb reset b side bus alarms: a 1 clears the alarms associated with the b side bus and spot alarms. this bit is self-clearing, and will reset to 0 after the reset cycle is completed. see note 2. 4restsp reset internal processor (spot): a 1 resets the spot processor, without affecting its ram. this bit will reset itself to 0 after the reset cycle is completed. see note 1. 3-1 unused unused: these bits must be written to 0. 0initsp initialize internal processor (spot) data ram: a 1 initializes the data ram associated with the spot processor and resets the general pur- pose registers of this processor. this bit should only be set to 1 after a hardware reset (lead 155 or c5) or a software reset (control bit reset above) has been activated. this bit is self-clearing and will reset to 0 after the data ram initialization is complete. see note 1. note 1: the control bits reset, restsp and initsp in address 015h should not be applied simultaneously, but only serially (e.g., 80h followed by 01h, rather than 81h). note 2: control bits restab and restbb may be applied at the same time (60h).
qe1m txc-04252 - 112 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. common registers - interrupt indication register descriptions address bit symbol description 020 7 int software interrupt indication: a 1 indicates that a latched alarm has occurred for which the corresponding interrupt mask bit(s) is/are set to 1. 6extck external clock interrupt indication: enabled when a 1 is written into the eckmsk bit. a 1 indicates that the external clock at input lead extck has failed (i.e., lextc=1). 5aside a side interrupt indication: enabled when a 1 is written into the asmsk bit. a 1 indicates that an alarm has occurred in one of the a-side alarm registers (i.e., 022h and 024h, bits 2, 1 and 0). 4bside b side interrupt indication: enabled when a 1 is written into the bsmsk bit. a 1 indicates that an alarm has occurred in one of the b-side alarm registers (i.e., 026h and 028h, bits 2, 1 and 0). 3port4 port 4 interrupt indication: enabled when a 1 is written into the p4msk bit. a 1 indicates that an alarm has occurred in one of the port 4 alarm registers for which the corresponding additional interrupt mask bit is also set to 1 (addresses 017h, 018h and 019h). 2port3 port 3 interrupt indication: enabled when a 1 is written into the p3msk bit. a 1 indicates that an alarm has occurred in one of the port 3 alarm registers for which the corresponding additional interrupt mask bit is also set to 1 (addresses 017h, 018h and 019h). 1port2 port 2 interrupt indication: enabled when a 1 is written into the p2msk bit. a 1 indicates that an alarm has occurred in one of the port 2 alarm registers for which the corresponding additional interrupt mask bit is also set to 1 (addresses 017h, 018h and 019h). 0port1 port 1 interrupt indication: enabled when a 1 is written into the p1msk bit. a 1 indicates that an alarm has occurred in one of the port 1 alarm registers for which the corresponding additional interrupt mask bit is also set to 1 (addresses 017h, 018h and 019h).
qe1m txc-04252 - 113 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. common registers - interrupt mask descriptions address bit symbol description 016 7-1 unused unused : these bits must be written to 0. 0sptmsk spot status interrupt mask: a 1 enables a hardware interrupt (lead int/irq ) and a software interrupt indication (int) when a spot alarm has occurred in any of the spot alarm register bits (address 028h, bits 7, 6 and 4). a 0 disables the spot alarms from causing an interrupt. see note 1. 017 7, 5, 3, 1 rptna (n=4-1) receive a side status interrupt mask bit: a 1 enables a hardware interrupt and software interrupt indication (int) when an alarm has occurred in an a-side port n alarm register while pnmsk is set for port n. a 0 disables the a side receive alarms for port n from causing an inter- rupt. see note 1. 6, 4, 2, 0 rptnb (n=4-1) receive b side status interrupt mask bit : a 1 enables a hardware interrupt and software interrupt indication (int) when an alarm has occurred in a b-side port n alarm register while pnmsk is set for port n. a 0 disables the b side receive alarms for port n from causing an inter- rupt . see note 1. 018 7, 5, 3, 1 tfifona (n=4-1) transmit fifo error a side status interrupt mask bit : a 1 enables a hardware interrupt and software interrupt indication (int) when an alarm has occurred for an a-side port n transmit fifo while pnmsk is set for port n. a 0 disables a transmit fifo error a side alarm for port n from causing an interrupt. see note 1. 6, 4, 2, 0 tfifonb (n=4-1) transmit fifo error b side status interrupt mask bit : a 1 enables a hardware interrupt and software interrupt indication (int) when an alarm has occurred for a b-side port n transmit fifo while pnmsk is set for port n. a 0 disables a transmit fifo error b side alarm for port n from causing an interrupt. see note 1. 019 7, 6, 5, 4 tportn (n=4-1) transmit status interrupt mask bit : a 1 enables a hardware interrupt and software interrupt indication (int) when an alarm has occurred for one of the port n transmit alarms while pnmsk is set for port n. a 0 dis- ables a transmit alarm from causing an interrupt. see note 1. 3, 2, 1, 0 rfifon (n=4-1) receive fifo error status interrupt mask bit : a 1 enables a hardware interrupt and software interrupt indication (int) when an alarm has occurred for a port n receive fifo while pnmsk is set for port n. a 0 dis- ables a receive fifo error alarm for port n from causing an interrupt. see note 1. note 1: please refer to the tables in the operation - interrupt structure section for the specific alarms and register locations to which these interrupt masks apply. rptna or rptnb is not required to be set to 1 to enable an interrupt for anrfi or bnrfi alarms. control bit hdwie must be set to 1 if a hardware interrupt is required.
qe1m txc-04252 - 114 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 021 7 unused unused: this bit must be written to 0. 6eckmsk external clock interrupt mask bit: a 1 enables a hardware interrupt and software interrupt indications (int and etxck) when an external clock failure alarm has occurred. see note 1. 5 asmsk a side interrupt mask bit : a 1 enables the a side interrupt indication (aside). see note 1. 4 bsmsk b side interrupt mask bit: a 1 enables the b side interrupt indication (bside). see note 1. 3p4msk port 4 interrupt mask bit : a 1 enables the port 4 interrupt indication (port4). it permits a hardware interrupt and a software interrupt indica- tion (int) when an alarm has occurred in one of the alarm registers for port 4, when the corresponding rpt4a, rpt4b, tfifo4a, tfifo4b, rfifo4 or tport4 mask bit is set to 1. see note 1. 2p3msk port 3 interrupt mask bit : a 1 enables the port 3 interrupt indication (port3). it permits a hardware interrupt and a software interrupt indica- tion (int) when an alarm has occurred in one of the alarm registers for port 3, when the corresponding rpt3a, rpt3b, tfifo3a, tfifo3b, rfifo3 or tport3 mask bit is set to 1. see note 1. 1p2msk port 2 interrupt mask bit : a 1 enables the port 2 interrupt indication (port2). it permits a hardware interrupt and a software interrupt indica- tion (int) when an alarm has occurred in one of the alarm registers for port 2, when the corresponding rpt2a, rpt2b, tfifo2a, tfifo2b, rfifo2 or tport2 mask bit is set to 1. see note 1. 0p1msk port 1 interrupt mask bit : a 1 enables the port 1 interrupt indication (port1). it permits a hardware interrupt and a software interrupt indica- tion (int) when an alarm has occurred in one of the alarm registers for port 1, when the corresponding rpt1a, rpt1b, tfifo1a, tfifo1b, rfifo1 or tport1 mask bit is set to 1. see note 1. note 1: please refer to the tables in the operation - interrupt structure section for the specific alarms and register locations to which these interrupt masks apply. rptna or rptnb is not required to be set to 1 to enable an interrupt for anrfi or bnrfi alarms. control bit hdwie must be set to 1 if a hardware interrupt is required. address bit symbol description
qe1m txc-04252 - 115 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. a/b drop and add bus - status register descriptions address bit symbol description 022 7-0 same bit definitions as in register 023 hex, except the bits are latched. 023 7 adloc a drop bus loss of clock: a 1 indicates that the a drop bus has detected a loss of clock. an alarm occurs when the input drop clock is stuck high or low for 1000 ns +/- 500 ns. recovery to 0 occurs on the first clock transition. please note that an alarm will force the add bus data and parity bits to a high impedance state, and will set the add indicator off for the duration of the alarm, when the drop bus timing mode is selected. 6aaloc a add bus loss of clock: a 1 indicates that the a add bus has detected a loss of clock, when add bus timing is selected. a loss of clock alarm forces the add bus data and parity bit to a high impedance state, and sets the add indicator off for the duration of the alarm. an alarm occurs when the input add clock is stuck high or low for 1000 ns +/- 500 ns. recovery to 0 occurs on the first clock transition. 5adpar a drop bus parity error detected: a 1 indicates that an even or odd parity error has been detected in the a drop bus signals. other than an alarm indication, no action is taken. parity is monitored for each drop bus clock cycle. 4-3 unused unused: these bits read out as 0. 2a3uaisi a side received upstream ais indication - au-3 c/sts-1 no. 3: when control bit se1ais is 0, a 1 indicates that ais has been detected in the h1/h2 bytes for au-3 c/sts-1 no. 3. when control bit se1ais is 1, a 1 indicates that ais has been detected in the e13 byte for au-3 c/sts-1 no. 3. disabled when the format is an au-4 vc-4, or sts-1. 1a2uaisi a side received upstream ais indication - au-3 b/sts-1 no. 2: when control bit se1ais is 0, a 1 indicates that ais has been detected in the h1/h2 bytes for au-3 b/sts-1 no. 2. when control bit se1ais is 1, a 1 indicates that ais has been detected in the e12 byte for au-3 b/sts-1 no. 2. disabled when the format is an au-4 vc-4, or sts-1. 0a1uaisi a side received upstream ais indication - au-3 a/sts-1 no. 1, au-4 vc-4, or sts-1: when control bit se1ais is 0, a 1 indicates that ais has been detected in the h1/h2 bytes for au-3 a/sts-1 no. 1, or in the au-4 vc-4 signal. when control bit se1ais is 1, a 1 indicates that ais has been detected in the e11 byte for au-3 a/sts-1 no. 1, au-4 vc-4, or the sts-1 signal. 024 7-0 same bit definitions as in register 025 hex, except the bits are latched.
qe1m txc-04252 - 116 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 025 7 lextc loss of external clock: a 1 indicates an external loss of clock alarm when the external clock (present on lead 138) is stuck high or low for 1000 ns +/- 500 ns. recovery to 0 occurs on the first clock transition. 6-3 unused unused: these bits read out as 0. 2 a3dh4e a drop bus loss of h4 indication - au-3 c/sts-1 no. 3: loss of mul- tiframe for au-3 c/sts-1 no. 3 is declared if one or more h4 values dif- fer from those of a two-bit counter once per multiframe for two consecutive multiframes, when control bit dv1sel is 0. the received h4 multiframe sequence is 00, 01, 10, and 11. the multiframe detector will continue to operate in a free running mode, but will lock to a new h4 sequence after one multiframe sequence has been received correctly. this h4 detector is disabled when the format is an au-4 vc-4, or sts-1. this bit is forced to 1 at power-up. 1 a2dh4e a drop bus loss of h4 indication - au-3 b/sts-1 no. 2: loss of mul- tiframe for au-3 b/sts-1 no. 2 is declared if one or more h4 values dif- fer from those of a two-bit counter once per multiframe for two consecutive multiframes, when control bit dv1sel is 0. the received h4 multiframe sequence is 00, 01, 10, and 11. the multiframe detector will continue to operate in a free running mode, but will lock to a new h4 sequence after one multiframe sequence has been received correctly. this h4 detector is disabled when the format is an au-4 vc-4, or sts-1. this bit is forced to 1 at power-up. 0 a1dh4e a drop bus loss of h4 indication - au-3 a/sts-1 no. 1, au-4 vc-4, or sts-1: loss of multiframe for au-3 a/sts-1 no. 1, au-4 vc-4 or sts-1 is declared if one or more h4 values differ from those of a two-bit counter once per multiframe for two consecutive multiframes, when con- trol bit dv1sel is 0. the received h4 multiframe sequence is 00, 01, 10, and 11. the multiframe detector will continue to operate in a free running mode, but will lock to a new h4 sequence after one multiframe sequence has been received correctly. this bit is forced to 1 at power-up. 026 7-0 same bit definitions as in register 027 hex, except the bits are latched. address bit symbol description
qe1m txc-04252 - 117 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 027 7 bdloc b drop bus loss of clock: a 1 indicates that the b drop bus has detected a loss of clock. an alarm occurs when the input drop clock is stuck high or low for 1000 ns +/- 500 ns. recovery to 0 occurs on the first clock transition. please note that an alarm will force the add bus data and parity bits to a high impedance state, and will set the add indicator off for the duration of the alarm, when the drop bus timing mode is selected. 6baloc b add bus loss of clock: a 1 indicates that the b add bus has detected a loss of clock, when add bus timing is selected. a loss of clock alarm forces the add bus data and parity bit to a high impedance state, and sets the add indicator off for the duration of the alarm. an alarm occurs when the input drop clock is stuck high or low for 1000 ns +/- 500 ns. recovery to 0 occurs on the first clock transition. 5bdpar b drop bus parity error detected: a 1 indicates that an even or odd parity error has been detected in the b drop bus signals. other than an alarm indication, no action is taken. parity is monitored for each drop bus clock cycle. 4-3 unused unused: these bits read out as 0. 2b3uaisi b side received upstream ais indication - au-3 c/sts-1 no. 3: when control bit se1ais is 0, a 1 indicates that ais has been detected in the h1/h2 bytes for au-3 c/sts-1 no. 3. when control bit se1ais is 1, a 1 indicates that ais has been detected in the e13 byte for au-3 c/sts-1 no. 3. disabled when the format is a au-4 vc-4, or sts-1. 1b2uaisi b side received upstream ais indication - au-3 b/sts-1 no. 2: when control bit se1ais is 0, a 1 indicates that ais has been detected in the h1/h2 bytes for au-3 b/sts-1 no. 2. when control bit se1ais is 1, a 1 indicates that ais has been detected in the e12 byte for au-3 b/sts-1 no. 2. disabled when the format is a au-4 vc-4, or sts-1 0b1uaisi b side received upstream ais indication - au-3 a/sts-1 no. 1, au-4 vc-4, or sts-1: when control bit se1ais is 0, a 1 indicates that ais has been detected in the h1/h2 bytes for au-3 a/sts-1 no. 1, or in the au-4 vc-4 signal. when control bit se1ais is 1, a 1 indicates that ais has been detected in the e11 byte for au-3 a/sts-1 no. 1, au-4 vc-4, or the sts-1 signal. 028 7-0 same bit definitions as in register 029 hex, except the bits are latched. address bit symbol description
qe1m txc-04252 - 118 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. port n - desynchronizer control register descriptions 029 7 sptloc internal processor (spot) loss of clock: the 29.16 mhz clock inter- nally derived from the 58.32 mhz desynchronizer clock input (extck) is monitored for loss of clock. loss of clock is declared if this clock is stuck high or low for 1000 +/- 500 ns. recovery to 0 occurs on the first clock transition. 6wdtexp watch dog timer expired: this bit is set to 1 when the spot is unable to service all requests in a timely manner. 5unused unused: this bits reads out as 0. 4perr parity error: this bit is set to 1 when a parity error is detected while reading the instruction ram of the spot. 3unused unused: this bits reads out as 0. 2 b3dh4e b drop bus loss of h4 indication - au-3 c/sts-1 no. 3: loss of mul- tiframe for au-3 c/sts-1 no. 3 is declared if one or more h4 values dif- fer from those of a two-bit counter once per multiframe for two consecutive multiframes, when control bit dv1sel is 0. the received h4 multiframe sequence is 00, 01, 10, and 11. the multiframe detector will continue to operate in a free running mode, but will lock to a new h4 sequence after one multiframe sequence has been received correctly. this h4 detector is disabled when the format is an au-4 vc-4, or sts-1. this bit is forced to 1 at power-up. 1 b2dh4e b drop bus loss of h4 indication - au-3 b/sts-1 no. 2: loss of mul- tiframe for au-3 b/sts-1 no. 2 is declared if one or more h4 values dif- fer from those of a two-bit counter once per multiframe for two consecutive multiframes, when control bit dv1sel is 0. the received h4 multiframe sequence is 00, 01, 10, and 11. the multiframe detector will continue to operate in a free running mode, but will lock to a new h4 sequence after one multiframe sequence has been received correctly. this h4 detector is disabled when the format is an au-4 vc-4, or sts-1. this bit is forced to 1 at power-up. 0 b1dh4e b drop bus loss of h4 indication - au-3 a/sts-1 no. 1, au-4 vc-4, or sts-1: loss of multiframe for au-3 a/sts-1 no. 1, au-4 vc-4 or sts-1 is declared if one or more h4 values differ from those of a two-bit counter once per multiframe for two consecutive multiframes, when con- trol bit dv1sel is 0. the received h4 multiframe sequence is 00, 01, 10, and 11. the multiframe detector will continue to operate in a free running mode, but will lock to a new h4 sequence after one multiframe sequence has been received correctly. this bit is forced to 1 at power-up. address bit symbol description 049 port 1 079 port 2 0a9 port 3 0d9 port 4 7-0 pointer leak rate value desynchronizer pointer leak rate register - port n: the count writ- ten into this location is used for the internal leak rate buffer, and repre- sents the average leak rate. a count of one represents 8 frames, or 2 multiframes, in the rate of occurrence of pointer movements from the number of counts read from the positive and negative stuff counters. address bit symbol description
qe1m txc-04252 - 119 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. port n - provisioning register descriptions address bit symbol description 04a port 1 07a port 2 0aa port 3 0da port 4 7 6 5 tnsel1 tnsel0 rnsel transmit port n a/b drop/add bus selection: the table below lists the selection criteria for the eight available modes of operation of port n: 7 6 5 operating mode 0 0 0 a drop only (drop) 0 0 1 b drop only (drop) 0 1 0 a drop a add (single unidirectional ring) 0 1 1 b drop b add (single unidirectional ring) 1 0 0 a drop b add (multiplexer) 1 0 1 b drop a add (multiplexer) 1 1 0 a drop a and b add (dual unidirectional ring) 1 1 1 b drop b and a add (dual unidirectional ring) 4 uchne unequipped channel for port n enabled: the uchne control bit works in conjunction with the uschne control bit (in bit position 3) according to the following table: uchne uschne action 0 x normal operation. 1 0 unequipped tu/vt generated. an unequipped tu/vt consists of a normal ndf, size bits equal to 10, a fixed pointer equal to 105, and all other bytes equal to 00h. 1 1 unequipped supervisory tu/vt generated. an unequipped supervisory tu/vt consists of a nor- mal ndf, size bits equal to 10, a fixed pointer equal to 105, and a valid j2 byte. the v5 byte will consist of a valid bip-2, with the signal label sent as zeros by setting control bit tntx label to 0. the n2 (z6) byte can be sent as zero by setting tcnen=0 and txb2dis=1. the k4 (z7) byte, bits 1, 2, 3, 4 and 8 can be sent as zeros by setting control bit tobwz=1. the rdi bits, v5 bit 8 and k4 (z7) bits 5, 6 and 7 can be disabled and sent as zeros by setting control bit rdien=0. note: x = don't care (0 or 1). 3 uschne unequipped supervisory channel for port n enabled: works in con- junction with the uchne bit according to the table given above. 2bypasn bypass codec of port n: a 1 disables the hdb3 codec (coder and decoder) of port n for nrz operation. a 0 enables the hdb3 codec. 1rnen receive port n enable: a 1 enables the receive data (nrz or rail) output and clock output for port n when lead quietn is low. a 0 forces the data and clock output leads to a high impedance state. the four bits power up as 0 and are reset to 0. a 1 must be written to these control bits to enable the port e1 outputs. 0 unused unused: this bit must be written to 0.
qe1m txc-04252 - 120 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 04b port 1 07b port 2 0ab port 3 0db port 4 7adnen a side drop bus port n tu/vt selection output enable: a 1 enables the drop bus adind signal output. this signal will be active low for the time slots corresponding to the tu/vt selected for port n. 6bdnen b side drop bus port n tu/vt selection output enable : a 1 enables the drop bus bdind signal output. this signal will be active low for the time slots corresponding to the tu/vt selected for port n. 5aanen a side add bus port n tu/vt selection output enable: a 1 enables the add bus aaind signal output. this signal will be active low for the time slots corresponding to the tu/vt selected for port n. 4banen b side add bus port n tu/vt selection output enable: a 1 enables the add bus baind signal output. this signal will be active low for the time slots corresponding to the tu/vt selected for port n. 3anantx prbs analyzer sampling tx e1 signal: a 1 enables the internal prbs analyzer to sample the tx e1 signal to be sent to the synchronizer. a 0 enables the internal prbs analyzer to sample the e1 signal to be sent to the rx e1 ports. 2ananen prbs analyzer enable: a1 enables the internal 2 15 -1 prbs analyzer. a 0 disables the analyzer. 1 prbsnen prbs generator enable: a 1 enables the internal 2 15 -1 prbs generator. a 0 disables the generator. 0 frdisn febe and rdi disabled for port n: enabled when the single unidirec- tional mode (control bits tnsel1, tnsel0 are equal to 01) is selected. a 1 disables receive side alarms or an out of range condition from generating an rdi. in addition, the rei (febe) value is transmitted as a zero. 04c port 1 07c port 2 0ac port 3 0dc port 4 7unused unused: this bit must be written to 0. 6-0 rtunn receive tu/vt selection for port n: the seven-bit binary code written into this location selects the tu/vt that is to be dropped from the a and/or b-side drop bus. control bits tsel1, tsel0 and rsel determine the drop bus(es) that the data is dropped from. if no tu/vt is selected, the microprocessor should either write a 1 to control bit rnais, thereby forcing an e1 ais, or should write a 0 to rnen, which will tristate the port n data and clock output leads. also, the febe and rdi values are transmitted as zero. 04d port 1 07d port 2 0ad port 3 0dd port 4 7unused unused: this bit must be written to 0. 6-0 ttunn transmit tu/vt selection for port n: the seven-bit binary code written into this location selects the tu/vt that is to be added to the a and/or b-side add bus. control bits tsel1, tsel0 and rsel determine the add bus(es) that the data is added to. if no tu/vt is selected, the a or b add bus will tristate. 0f1 7-4 unused unused: these bits must be written to 0. 3v4en v4en: a 1 enables the v4 access function in both receive and transmit directions. 2-0 unused unused: these bits must be written to 0. address bit symbol description
qe1m txc-04252 - 121 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. port n - receive status register and counter descriptions the following descriptions pertain to the status registers and counters assigned to port n. the status registers provide two readable bit positions per alarm. one bit (in an odd-numbered address) indicates the detected alarm as unlatched. the second bit (in the preceding even-numbered address) provides the alarm status as an latched alarm indication. a latched bit position is set on positive, negative, or both positive and negative transi- tions of the alarm, or on a positive level of the alarm. a latched alarm is cleared on a microprocessor read cycle of its address. during a read cycle for a counter, internal logic holds any increment to the counter until the read cycle is complete, and then updates the counter afterwards. 0f5 7 txb2dis transmit bip-2 disable (test bit): a 0 is used for normal operation and will allow the calculated n2 (z6) bip-2 and v5 bip-2 values to be transmit- ted. a 1 will disable n2 (z6) bip-2 calculation as well as v5 bip-2 calcula- tion for all 4 ports and output zeros in its place. 6-0 unused unused: these bits must be written to 0. address bit symbol description 030 port 1 060 port 2 090 port 3 0c0 port 4 7-0 latched an alarms same alarms as the unlatched indications in the following address loca- tions (7-0), except that these alarm states are latched. 031 port 1 061 port 2 091 port 3 0c1 port 4 7anais a drop bus port n tu/vt ais alarm: a 1 indicates that an ais has been detected in the v1/v2 pointer bytes for the tu/vt selected. 6anlop a drop bus port n loss of tu/vt pointer alarm: a 1 indicates that a loss of pointer has been detected in the v1/v2 pointer bytes for the tu/vt selected. 5ansize a drop bus port n tu/vt pointer size error indication: a 1 indicates that the receive size indicator in the pointer (bits 5 and 6 in the v1 pointer byte) is not 10 for the tu/vt selected. the detection and recov- ery time is immediate. 4 anndf a drop bus port n new data flag indication: a 1 indicates that a new data flag (1001 or 0001/1101/1011/1000) has been detected in the v1 pointer byte for the tu/vt selected (i.e., bits 1-4 in the v1 byte are the inverse of the normal 0110 pattern or differ in only one bit, with a correct size indicator and a valid pointer value). 3anrdis a drop bus port n remote server defect indication: a 1 indicates that either a remote server defect alarm has been detected (bits 5, 6 and 7 in k4 (z7) byte are equal to 101), or an rdi has been detected coming from older equipment (bit 8 in v5 byte equals 1 when bits 6 and 7 in k4 (z7) byte are equal to 00 or 11). the number of consecutive events used for detection and recovery is determined by control bit v5al10. 2anrfi a drop bus port n remote failure indication: a 1 indicates that bit 4 in the v5 byte is equal to 1 for the tu/vt selected. the detection and recovery time is immediate. address bit symbol description
qe1m txc-04252 - 122 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 031 port 1 061 port 2 091 port 3 0c1 port 4 (cont.) 1anuneq a drop bus port n unequipped indication: a 1 indicates that an unequipped status has been detected in the v5 signal label (bits 5-7 in v5 byte = 0) for the tu/vt selected in the a side drop bus. an unequipped signal label is equal to 000. five or more consecutive received unequipped signal labels will cause this alarm. recovery occurs when five or more consecutive signal labels are received not equal to 000. 0 ansler a drop bus port n signal label mismatch indication: a 1 indicates that the receive signal label (bits 5-7 in v5 byte) does not match the microprocessor-written signal label in the tu/vt selected for the a side drop bus. five or more consecutive signal label mismatches (against the microprocessor-written value), or received labels not equal to 001, results in an alarm. recovery occurs upon receipt of five or more con- secutive correct signal labels, or 001 values. 032 port 1 062 port 2 092 port 3 0c2 port 4 7-4 anpj counter a drop bus port n positive pointer justification counter: a four-bit counter that increments on a positive pointer movement for the tu/vt selected. the counter saturates at full count and is cleared when it is read. 3-0 annj counter a drop bus port n negative pointer justification counter: a four-bit counter that increments on a negative pointer movement for the tu/vt selected. the counter saturates at full count and is cleared when it is read. 033 port 1 063 port 2 093 port 3 0c3 port 4 7-0 anbip2 counter a drop bus port n bip-2 counter: an 8-bit counter which counts the number of bip-2 errors detected for the tu/vt selected. a maximum of two errors can occur each frame. these two errors cause a single count if the block control bit is set to 1. the counter saturates at full count and is cleared when it is read. 034 port 1 064 port 2 094 port 3 0c4 port 4 7-0 anfebe counter a drop bus port n febe counter: an 8-bit counter which counts the number of febe errors received (bit 3 in v5 byte = 1) for the tu/vt selected. the counter saturates at full count and is cleared when it is read. 035 port 1 065 port 2 095 port 3 0c5 port 4 7-3 unused unused: these bits read out as indeterminate. 2-0 an rx label a drop bus port n received signal label : these three bit positions correspond to the three signal label bits in bits 5 through 7 of the v5 byte in the tu/vt selected. this location is updated every 500 microseconds. bit 2 corresponds to bit 7 in the v5 byte. these bits are also compared against the microprocessor-written mismatch signal label bits for an unequipped and mismatch indication. code 1 (001) has been imple- mented in hardware and does not have to be written into this location. 04e port 1 07e port 2 0ae port 3 0de port 4 7-6 latched an alarms same alarms as the corresponding address 04f, 07f, 0af, 0df bit posi- tions, except that these alarms are latched. 5-4 unused unused: these bits read out as zero. 3-2 latched an alarms same alarms as the corresponding address 04f, 07f, 0af, 0df bit posi- tions, except that these alarms are latched. 1-0 unused unused: these bits read out as zero. address bit symbol description
qe1m txc-04252 - 123 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 04f port 1 07f port 2 0af port 3 0df port 4 7anrdip a drop bus port n remote payload defect indication: a 1 indicates that a remote payload defect alarm has been detected (bits 5, 6 and 7 in k4 (z7) byte are equal to 010). the number of consecutive events used for detection and recovery is determined by control bit v5al10. 6 anrdic a drop bus port n remote connectivity defect indication: a 1 indi- cates that a remote connectivity defect alarm has been detected (bits 5, 6 and 7 in k4 (z7) byte are equal to 110). the number of consecutive events used for detection and recovery is determined by control bit v5al10. 5-4 unused unused: these bits read out as zero. 3 anj2lol a drop bus port n j2 loss of lock alarm: enabled when control bit j2nsize is a 0, and control bit j2ncom is a 1. a 1 indication occurs when the alignment of the 16-byte j2 trace identifier label (message) has not been established. 2 anj2tim a drop bus port n j2 trail trace mismatch alarm: enabled when control bit j2nsize is a 0, and control bit j2ncom is a 1. a 1 indicates that the stable 16-byte message did not match for one message time. recovery occurs when the j2 state machine loses lock and then acquires lock with a 16-byte stable j2 message that matches the j2 comparison message written by the microprocessor. 1-0 unused unused: these bits read out as zero. 038 port 1 068 port 2 098 port 3 0c8 port 4 7-0 an receive k4 (z7) byte a drop bus port n receive k4 (z7) byte : the eight bits in this register position correspond to the k4 (z7) byte received in the tu/vt selected. bit 7 corresponds to bit 1 in the k4 (z7) byte. 039 port 1 069 port 2 099 port 3 0c9 port 4 7-0 an receive o-bits a drop bus port n receive o-bits : the two nibbles (bits 7-4 and 3-0) in this register correspond to the two sets of four overhead communication bits received in the tu/vt selected. bit 7 corresponds to bit 3 in the sec- ond justification control byte, while bit 0 corresponds to bit 6 in the first justification control byte. the two nibbles written into this register location will be from the same frame. 05a port 1 08a port 2 0ba port 3 0ea port 4 7-1 latched an alarms same alarms as the following address locations (7-1), except that these alarm states are latched. 0unused unused: this bit reads out as indeterminate. address bit symbol description
qe1m txc-04252 - 124 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 05b port 1 08b port 2 0bb port 3 0eb port 4 7 antcuq a drop bus port n tandem connection unequipped alarm: a tc unequipped alarm indication (a 1) occurs when bits 3 through 8 in the n2 (z6) byte are all equal to 0 for 5 or more consecutive frames. recovery to 0 occurs when bits 3 through 8 are not all equal to 0 for 5 or more con- secutive frames. 6antcais a drop bus port n tandem connection ais alarm: a tc ais alarm indication (a 1) occurs when bit 4 in the n2 (z6) byte is equal to 1 for five or more consecutive frames. recovery to 0 occurs when bit 4 is a 0 for five or more consecutive frames. 5antclm a drop bus port n tandem connection loss of multiframe alarm: a tc loss of multiframe alarm indication (a 1) occurs when four or more consecutive errored multiframes are detected in bits 7 and 8 in the n2 (z6) byte. recovery to 0 occurs when three consecutive non-errored multiframes (1111 1111 1111 1110) are detected. 4antcll a drop bus port n bus tandem connection trail trace message loss of lock alarm: an alarm indication (a 1) occurs when the align- ment of the 16-byte n2 (z6) tandem connection trace identifier label (message) has not been established. 3antctm a drop bus port n bus tandem connection trail trace message mismatch alarm: an alarm indication (a 1) indicates that the stable tan- dem connection 16-byte message did not match for one message time. recovery to 0 occurs when the n2 (z6) byte tc message state machine loses lock and then acquires lock with a 16-byte stable n2 (z6) byte message that matches the n2 (z6) byte comparison message written by the microprocessor. 2 antcodi a drop bus port n tandem connection odi alarm: a tc odi alarm indication (a 1) occurs when n2 (z6) byte bit 7 in frame 74 is equal to 1 for five or more consecutive frames. recovery to 0 occurs when bit 7 is a 0 for five or more consecutive frames. 1 antcrdi a drop bus port n tandem connection rdi alarm: a tc rdi alarm indication (a 1) occurs when n2 (z6) byte bit 8 in frame 73 is equal to 1 for five or more consecutive frames. recovery to 0 occurs when bit 8 is a 0 for five or more consecutive frames. 0unused unused: this bit reads out as indeterminate. 100 port 1 200 port 2 300 port 3 400 port 4 7-0 an tc bip-2 error counter a drop bus port n tandem connection bip-2 counter: an 8-bit counter which counts the number of bip-2 errors detected in the n2 (z6) byte for the tu/vt selected when the tandem connection feature is enabled. a maximum of two errors can be counted each frame. these two errors cause a single count if the block control bit is set to 1. the counter saturates at full count and is cleared when it is read. 101 port 1 201 port 2 301 port 3 401 port 4 7-0 an tc rei error counter a drop bus port n tandem connection rei counter: an 8-bit counter which counts the number of rei errors detected in bit 5 in the n2 (z6) byte for the tu/vt selected when the tandem connection feature is enabled. the counter saturates at full count and is cleared when it is read. address bit symbol description
qe1m txc-04252 - 125 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 102 port 1 202 port 2 302 port 3 402 port 4 7-0 an tc oei error counter a drop bus port n tandem connection oei counter: an 8-bit counter which counts the number of oei errors detected in bit 6 in the n2 (z6) byte for the tu/vt selected when the tandem connection feature is enabled. the counter saturates at full count and is cleared when it is read. 116 port 1 216 port 2 316 port 3 416 port 4 7-0 an receive v4 byte a drop bus port n receive v4 byte: when control bit v4en is 1, the eight bits in this register position correspond to the v4 byte received in the tu/vt selected. bit 7 corresponds to bit 1 in the v4 byte. 03a port 1 06a port 2 09a port 3 0ca port 4 7-0 latched bn alarms same alarms as the following address locations (7-0), except that these alarm states are latched. 03b port 1 06b port 2 09b port 3 0cb port 4 7bnais b drop bus port n tu/vt ais alarm: a 1 indicates that an ais has been detected in the v1/v2 pointer bytes for the tu/vt selected. 6bnlop b drop bus port n loss of tu/vt pointer alarm: a 1 indicates that a loss of pointer has been detected in the v1/v2 pointer bytes for the tu/vt selected. 5bnsize b drop bus port n tu/vt pointer size error indication: a 1 indicates that the receive size indicator in the pointer (bits 5 and 6 in the v1 pointer byte) is not 10 for the tu/vt selected. the detection and recov- ery time is immediate. 4 bnndf b drop bus port n new data flag indication: a 1 indicates that a new data flag (1001 or 0001/1101/1011/1000) has been detected in the v1 pointer byte for the tu/vt selected (i.e., bits 1-4 in the v1 byte are the inverse of the normal 0110 pattern or differ in only one bit, with a correct size indicator and a valid pointer value). 3bnrdis b drop bus port n remote server defect indication: a 1 indicates that either a remote server defect alarm has been detected (bits 5, 6 and 7 in k4 (z7) byte are equal to 101), or an rdi has been detected coming from older equipment (bit 8 in v5 byte equals 1 when bits 6 and 7 in k4 (z7) byte are equal to 00 or 11). the number of consecutive events used for detection and recovery is determined by control bit v5al10. 2bnrfi b drop bus port n remote failure indication: a 1 indicates that bit 4 in the v5 byte is equal to 1 for the tu/vt selected. the detection and recovery time is immediate. address bit symbol description
qe1m txc-04252 - 126 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 03b port 1 06b port 2 09b port 3 0cb port 4 (cont.) 1bnuneq b drop bus port n unequipped indication: a 1 indicates that an unequipped status has been detected in the v5 signal label (bits 5-7 in v5 byte = 0) for the tu/vt selected in the b side drop bus. an unequipped signal label is equal to 000. five or more consecutive received unequipped signal labels will cause this alarm. recovery occurs when five or more consecutive signal labels are received not equal to 000. 0 bnsler b drop bus port n signal label mismatch indication: a 1 indicates that the receive signal label (bits 5-7 in v5 byte) does not match the microprocessor-written signal label in the tu/vt selected for the b side drop bus. five or more consecutive signal label mismatches (against the microprocessor-written value), or received labels not equal to 001, results in an alarm. recovery occurs upon receipt of five or more con- secutive correct signal labels, or 001 values. 03c port 1 06c port 2 09c port 3 0cc port 4 7-4 bnpj counter b drop bus port n positive pointer justification counter: a four-bit counter that increments on a positive pointer movement for the tu/vt selected. the counter saturates at full count and is cleared when it is read. 3-0 bnnj counter b drop bus port n negative pointer justification counter: a four-bit counter that increments on a negative pointer movement for the tu/vt selected. the counter saturates at full count and is cleared when it is read. 03d port 1 06d port 2 09d port 3 0cd port 4 7-0 bnbip2 counter b drop bus port n bip-2 counter: an 8-bit counter which counts the number of bip-2 errors detected for the tu/vt selected. a maximum of two errors can occur each frame. these two errors cause a single count if the block control bit is set to 1. the counter saturates at full count and is cleared when it is read. 03e port 1 06e port 2 09e port 3 0ce port 4 7-0 bnfebe counter b drop bus port n febe counter: an 8-bit counter which counts the number of febe errors received (bit 3 in v5 byte = 1) for the tu/vt selected. the counter saturates at full count and is cleared when it is read. 03f port 1 06f port 2 09f port 3 0cf port 4 7-3 unused unused: these bits read out as indeterminate. 2-0 bn rx label b drop bus port n received signal label: these three bit positions correspond to the three signal label bits located in bits 5 through 7 of the v5 byte for the tu/vt selected. this location is updated every 500 microseconds. bit 2 corresponds to bit 7 in the v5 byte. these bits are also compared against the microprocessor-written mismatch signal label bits for an unequipped and mismatch indication. code 1 (001) has been implemented in hardware and does not have to be written into this loca- tion. 05e port 1 08e port 2 0be port 3 0ee port 4 7-6 latched bn alarms same alarms as the corresponding address 05f, 08f, 0bf, 0ef bit posi- tions except that these alarms are latched. 5-4 unused unused: these bits read out as zero. 3-2 latched bn alarms same alarms as the corresponding address 05f, 08f, 0bf, 0ef bit posi- tions except that these alarms are latched. 1-0 unused unused: these bits read out as zero. address bit symbol description
qe1m txc-04252 - 127 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 05f port 1 08f port 2 0bf port 3 0ef port 4 7bnrdip b drop bus port n remote payload defect indication: a 1 indicates that a remote payload defect alarm has been detected (bits 5, 6 and 7 in k4 (z7) byte are equal to 010). the number of consecutive events used for detection and recovery is determined by control bit v5al10. 6 bnrdic b drop bus port n remote connectivity defect indication: a 1 indi- cates that a remote connectivity defect alarm has been detected (bits 5, 6 and 7 in k4 (z7) byte are equal to 110). the number of consecutive events used for detection and recovery is determined by control bit v5al10. 5-4 unused unused: these bits read out as zero. 3 bnj2lol b drop bus port n j2 loss of lock alarm: enabled when control bit j2nsize is a 0, and control bit j2ncom is a 1. a 1 indication occurs when the alignment of the 16-byte j2 trace identifier label (message) has not been established. 2 bnj2tim b drop bus port n j2 trail trace mismatch alarm: enabled when control bit j2nsize is a 0, and control bit j2ncom is a 1. a 1 indicates that the stable 16-byte message did not match for one message time. recovery occurs when the j2 state machine loses lock and then acquires lock with a 16-byte stable j2 message that matches the j2 comparison message written by the microprocessor. 1-0 unused unused: these bits read out as zero. 042 port 1 072 port 2 0a2 port 3 0d2 port 4 7-0 bn receive k4 (z7) byte b drop bus port n receive k4 (z7) byte: the eight bits in this register position correspond to the k4 (z7) byte received for the tu/vt selected. bit 7 corresponds to bit 1 in the k4 (z7) byte. 043 port 1 073 port 2 0a3 port 3 0d3 port 4 7-0 bn receive o-bits b drop bus port n receive o-bits: the two nibbles (bits 7-4 and 3-0) in this register correspond to the two sets of four overhead communica- tion bits received in the tu/vt selected. bit 7 corresponds to bit 3 in the second justification control byte, while bit 0 corresponds to bit 6 in the first justification control byte. the two nibbles written into this register location will be from the same frame. 05c port 1 08c port 2 0bc port 3 0ec port 4 7-1 latched bn alarms same alarms as the following address locations (7-1), except that these alarm states are latched. 0unused unused: this bit reads out as indeterminate. address bit symbol description
qe1m txc-04252 - 128 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 05d port 1 08d port 2 0bd port 3 0ed port 4 7 bntcuq b drop bus port n tandem connection unequipped alarm: a tc unequipped alarm indication (a 1) occurs when bits 3 through 8 in the n2 (z6) byte are all equal to 0 for 5 or more consecutive frames. recovery to 0 occurs when bits 3 through 8 are not all equal to 0 for 5 or more con- secutive frames. 6bntcais b drop bus port n tandem connection ais alarm: a tc ais alarm indication (a 1) occurs when bit 4 in the n2 (z6) byte is equal to 1 for five or more consecutive frames. recovery to 0 occurs when bit 4 is a 0 for five or more consecutive frames. 5bntclm b drop bus port n tandem connection loss of multiframe alarm: a tc loss of multiframe alarm indication (a 1) occurs when four or more consecutive errored multiframes are detected in bits 7 and 8 in the n2 (z6) byte. recovery to 0 occurs when three consecutive non-errored multiframes (1111 1111 1111 1110) are detected. 4bntcll b drop bus port n bus tandem connection trail trace message loss of lock alarm: an alarm indication (a 1) occurs when the align- ment of the 16-byte n2 (z6) tandem connection trace identifier label (message) has not been established. 3bntctm b drop bus port n bus tandem connection trail trace message mismatch alarm: an alarm indication (a 1) indicates that the stable tan- dem connection 16-byte message did not match for one message time. recovery to 0 occurs when the n2 (z6) byte tc message state machine loses lock and then acquires lock with a 16-byte stable n2 (z6) byte message that matches the n2 (z6) byte comparison message written by the microprocessor. 2 bntcodi b drop bus port n tandem connection odi alarm: a tc odi alarm indication (a 1) occurs when n2 (z6) byte bit 7 in frame 74 is equal to 1 for five or more consecutive frames. recovery to 0 occurs when bit 7 is a 0 for five or more consecutive frames. 1 bntcrdi b drop bus port n tandem connection rdi alarm: a tc rdi alarm indication (a 1) occurs when n2 (z6) byte bit 8 in frame 73 is equal to 1 for five or more consecutive frames. recovery to 0 occurs when bit 8 is a 0 for five or more consecutive frames. 0unused unused: this bit reads out as indeterminate. 180 port 1 280 port 2 380 port 3 480 port 4 7-0 bn tc bip-2 error counter b drop bus port n tandem connection bip-2 counter: an 8-bit counter which counts the number of bip-2 errors detected in the n2 (z6) byte for the tu/vt selected when the tandem connection feature is enabled. a maximum of two errors can be counted each frame. these two errors cause a single count if the block control bit is set to 1. the counter saturates at full count and is cleared when it is read. 181 port 1 281 port 2 381 port 3 481 port 4 7-0 bn tc rei error counter b drop bus port n tandem connection rei counter: an 8-bit counter which counts the number of rei errors detected in bit 5 in the n2 (z6) byte for the tu/vt selected when the tandem connection feature is enabled. the counter saturates at full count and is cleared when it is read. address bit symbol description
qe1m txc-04252 - 129 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 182 port 1 282 port 2 382 port 3 482 port 4 7-0 bn tc oei error counter b drop bus port n tandem connection oei counter: an 8-bit counter which counts the number of oei errors detected in bit 6 in the n2 (z6) byte for the tu/vt selected when the tandem connection feature is enabled. the counter saturates at full count and is cleared when it is read. 196 port 1 296 port 2 396 port 3 496 port 4 7-0 bn receive v4 byte b drop bus port n receive v4 byte: when control bit v4en is 1, the eight bits in this register position correspond to the v4 byte received in the tu/vt selected. bit 7 corresponds to bit 1 in the v4 byte. 044 port 1 074 port 2 0a4 port 3 0d4 port 4 7 rnffe same alarms as the corresponding address 045, 075, 0a5 and 0d5 bits, except that these alarm states are latched. 6unused unused: this bit reads out as 0. 5-0 latched tx alarms same alarms as the corresponding address 045, 075, 0a5 and 0d5 bits, except that these alarm states are latched. 045 port 1 075 port 2 0a5 port 3 0d5 port 4 7 rnffe receive port n fifo error: a 1 indicates that the receive fifo for port 1 has overflowed or underflowed. the fifo is reset automatically. other than an alarm indication, no action is taken. 6unused unused: this bit reads out as 0. 5ananool prbs analyzer out of lock: a 1 indicates that the internal prbs ana- lyzer is out of lock. 4tanfe transmit a add bus port n fifo error: a 1 indicates that the a add bus fifo has overflowed or underflowed. the fifo is recentered and is held reset for up to two multiframes automatically. the vt ais payload will be transmitted via the add bus when the fifo error occurs. 3tbnfe transmit b add bus port n fifo error: a 1 indicates that the b add bus fifo has overflowed or underflowed. the fifo is recentered and is held reset for up to two multiframes automatically. the vt ais payload will be transmitted via the add bus when the fifo error occurs. 2 tnlos transmit port n loss of signal: an alarm occurs when there are no signal transitions detected on the positive rail or negative rail for a period of 256 consecutive pulse positions. recovery occurs when there are at least 32 transitions counted for 256 consecutive pulse positions. for an nrz signal, this alarm is active when a low occurs on the external trans- mit loss of signal indication lead tlosn , which is shared with the tnin lead. 1tnloc transmit port n loss of clock: a 1 indicates that the transmit clock (tcin) for port n has stuck high or low for 6 or more clock cycles. recov- ery occurs on the first clock transition. 0tndais transmit port n ais detected: a 1 indicates that line ais (one or less zero in 256 bits) has been detected in the bit stream for port n. recovery occurs when there are 3 or more zeros in 256 bits. other than reporting the alarm, no action is taken. address bit symbol description
qe1m txc-04252 - 130 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 046 port 1 076 port 2 0a6 port 3 0d6 port 4 7-0 coding violation counter low order byte transmit port n coding violation counter: low order byte of a 16-bit saturating counter which counts the number of coding errors that have occurred in the hdb3 line code. during a read cycle, internal logic holds any new count until the read cycle is complete, and then the counter is updated. this counter is cleared on a reset pulse, any reset, rnsets or rnsetc control bit = 1, or when its low order byte is read. this low order byte must be read before the high order byte for the same port, which is located in the following address. 047 port 1 077 port 2 0a7 port 3 0d7 port 4 7-0 coding violation counter high order byte transmit port n coding violation counter: high order byte of an 16-bit saturating counter which counts the number of coding errors that have occurred in the hdb3 line codes. during a read cycle, internal logic holds any new count until the read cycle is complete, and then the counter is updated. this counter is cleared on a reset pulse, any reset, rnsets or rnsetc control bit = 1, or when its low order byte is read. this high order byte must be read after the low order byte for the same port, which is located in the preceding address, but before the next read of the low order byte for any port. (reading the low order byte for any port causes a simultaneous transfer of the contents of the high order byte for the same port into a high order byte memory location that is common to all four ports. when any high order byte is read, the data out- put from the high order byte address is the content of this common mem- ory location, not the current content of the addressed high order byte.) address bit symbol description
qe1m txc-04252 - 131 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. port n - operation register descriptions address bit symbol description 048 port 1 078 port 2 0a8 port 3 0d8 port 4 7-5 unused unused: these bits must be written to 0. 4 1bnrdi 1-bit/3-bit rdi selection for port n: when set to 0, the selected port will function as a 3-bit enhanced rdi. when set to a 1, the selected port will function as 1-bit rdi. 3 j2nten j2 transmit message enable for port n: a 1 enables a microproces- sor-written message to be transmitted. a 0 disables the transmission of the j2 message from ram. instead, the j2 byte is transmitted as 00h. 2j2nsize j2 message size segment for port n: works in conjunction with the j2ncom bit according to the following table: j2nsize j2ncom action 0 0 transmit and receive j2 message segments are configured for a 16-byte message size. micropro- cessor reads 16-byte segment. j2 comparison circuit and alarms are disabled. 0 1 transmit and receive j2 message segments are configured for a 16-byte message size. trail trace message comparison circuit enabled. 1 x transmit and receive j2 message segments are configured for a 64-byte message size. micropro- cessor reads 64-byte segment. j2 comparison circuit and alarms are disabled. the tandem connection feature must be disabled by setting tcnen=0. 1 j2ncom j2 message comparison enable bit for port n: works in conjunction with the j2nsize control bit according to the table given above. 0j2naise j2 ais/rdi/tc alarm enable for port n: a 1 enables receive e1 ais, a remote connectivity defect indication, and both of the tc alarms (tcn- odi, tcnrdi) to be transmitted when either an anj2tim/bnj2tim or an anj2lol/bnj2lol occurs. the ais, rdi and tc alarm generated depend on the bus side selected.
qe1m txc-04252 - 132 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 050 port 1 080 port 2 0b0 port 3 0e0 port 4 7fnlbk facility loopback: a 1 enables an e1 facility (side) loopback for port n. the e1 transmit clock and data output signals are looped back internally as the e1 receive clock and data input signals. the external e1 receive input signals are disabled. the e1 transmit clock and data output signals are pro- vided at the interface. 6 lnlbk line loopback: a 1 enables an e1 line (side) loopback for port n. the receive e1 clock and data output signals are looped back internally as the e1 transmit input signals. the external e1 transmit clock and data input sig- nals are disabled. the e1 receive clock and data output signals are pro- vided at the interface. 5rnais send receive e1 line ais for port n: a 1 enables an e1 ais (unframed all ones signal) to be inserted into the receive data stream for port n inde- pendent of the status of the internal alarms. 4tnais transmit e1 line ais for port n: a 1 enables an e1 ais (unframed all ones signal) to be inserted into the transmit data stream for port n indepen- dent of the status of the internal alarms. 3tnvtais transmit vt ais for the tu/vt selected for port n: a 1 enables a tu/vt ais to be transmitted for the tu/vt selected. a tu/vt ais consists of all ones in the entire tu/vt, including bytes v1 through v4. 2tnrfi transmit port n rfi (remote failure indication): a 1 enables an rfi alarm to be transmitted (bit 4 in the v5 byte is set to 1). 1tnrdis transmit port n rdis (remote server defect indication): a 1 enables an rdis to be transmitted (bit 8 in the v5 byte is set to 1, and bits 5, 6 and 7 in the k4 (z7) byte are set to 101). 0tnrdip transmit port n rdip (remote payload defect indication): a 1 enables an rdip to be transmitted (bit 8 in the v5 byte is set to 0, and bits 5, 6 and 7 in the k4 (z7) byte are set to 010). address bit symbol description
qe1m txc-04252 - 133 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 051 port 1 081 port 2 0b1 port 3 0e1 port 4 7 tcnrdi tandem connection rdi generation for port n: a 1 enables a tc rdi to be generated (bit 8 in frame 73 is a 1). 6tcnodi tandem connection odi generation for port n: a 1 enables a tc odi to be generated (bit 7 in frame 74 is a 1). 5tcnais tandem connection ais indication transmitted for port n: a 1 enables a tc ais indication to be generated (bit 4 in the n2 (z6) byte is a 1). 4tcnen tandem connection feature enable for port n: a 1 enables the tu tan- dem connection feature (j2nsize must be 0). a 0 disables the tandem connection feature. in the receive direction all tc alarms are disabled. in the transmit direction, bits 3 through 8 in the n2(z6) byte are transmitted as 0 while bits 1 and 2 still contain the calculated bip-2. 3 tcnre tandem connection remote defect indication enable for port n: as explained in note1, a 1 enables internal defined tandem connection alarms to send a tc rdi (bit 8 in frame 73). for example, a tc rdi for port 1 is generated: - when tc enable (tc1en) and tc rdi enable (tc1re) are 1 and any of: - loss of pointer alarm (a1lop, b1lop) - tu ais alarm (a1ais, b1ais) - drop bus ais alarm (asuasi, bsuasi) when heaise is 1 - drop bus h4 alarm (asdh4e, bsdh4e) when dv1sel is 1 - unequipped signal label (a1uneq, b1uneq) when uqae is 1 - mismatch signal label (a1sler, b1sler) - j2 loss of lock alarm (a1j2lol, b1j2lol) when j2aisen is 1 - j2 mismatch alarm (a1j2tim, b1j2tim) when j2aisen is 1 - tc unequipped alarm (a1tcuq, b1tcuq) - tc loss of lock alarm (a1tcll, b1tcll) - tc mismatch alarm (a1tctm, b1tctm) - tc loss of multiframe alarm (a1tclm, b1tclm) - a 1 written to tc1rdi - when tc enable (tc1en) is a 1 and tc rdi enable (tc1re) is 0 and: - a 1 written to tc1rdi. note 1: in determining whether to send tc odi or tc rdi, it is necessary to sample certain alarm conditions. since tc odi or tc rdi are sent only once for every 38 ms multiframe, it is conceivable that these alarms may tog- gle more than one time in this interval. therefore, all the alarms needed to generate tc odi or tc rdi are sampled during every 500 s multiframe, setting the tc odi or tc rdi alarm. address bit symbol description
qe1m txc-04252 - 134 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 051 port 1 081 port 2 0b1 port 3 0e1 port 4 (cont.) 2tcnoe tandem connection outgoing defect indication enable for port n: as explained in note 1, a 1 enables internal defined tandem connection alarms to send a tc odi (bit 7 in frame 74). for example, a tc odi for port 1 is generated: - when tc enable (tc1en) and tc odi enable (tc1oe) are 1 and any of: - loss of pointer alarm (a1lop, b1lop) - tu ais alarm (a1ais, b1ais) - drop bus ais alarm (asuasi, bsuasi) when heaise is 1 - drop bus h4 alarm (asdh4e, bsdh4e) when dv1sel is 1 - unequipped signal label (a1uneq, b1uneq) when uqae is 1 - mismatch signal label (a1sler, b1sler) - j2 loss of lock alarm (a1j2lol, b1j2lol) when j2aisen is 1 - j2 mismatch alarm (a1j2tim, b1j2tim) when j2aisen is 1 - tc unequipped alarm (a1tcuq, b1tcuq) - tc ais alarm (a1tcais, b1tcais) - tc loss of lock alarm (a1tcll, b1tcll) - tc mismatch alarm (a1tctm, b1tctm) - tc loss of multiframe alarm (a1tclm, b1tclm) - a 1 written to tc1odi. (where s is the sts-1 or au-3 identifier, 1-3) - when tc enable (tc1en) is a 1 and tc odi enable (tc1oe) is 0 and: - a 1 written to tc1odi. 1 tcnaen tandem connection line ais enable for port n: a 1 enables internal receive tc alarms to generate receive e1 line ais. 0 tnrdic transmit port n rdic (remote connectivity defect indication): a 1 enables an rdic to be transmitted (bit 8 in the v5 byte is set to 1, and bits 5, 6 and 7 in the k4 (z7) byte are set to 110). 052 port 1 082 port 2 0b2 port 3 0e2 port 4 7rnsets reset port n selected functions: a 1 will clear the alarms, reset the per- formance counters to 0, and re-initialize the fifos associated with port n. the control bits for port n are not reset. this bit is self-clearing, and will reset to 0 after the reset cycle is completed. 6rnsetc reset port n performance counters: a 1 resets the performance counters to 0 for port n. this bit is self-clearing, and will reset to 0 after the reset cycle is completed. 5-2 unused unused: these bits must be written to 0. 1tnfb2 transmit port n bip-2 error mask (force bip-2 error): a 1 causes bits 1 and 2 (the bip-2 value) in the v5 byte to be inverted from the calculated value and transmitted for one frame. this bit is self-clearing, and will reset to 0 after the single error is transmitted. note 1: in determining whether to send tc odi or tc rdi, it is necessary to sample certain alarm conditions. since tc odi or tc rdi are sent only once for every 38 ms multiframe, it is conceivable that these alarms may tog- gle more than one time in this interval. therefore, all the alarms needed to generate tc odi or tc rdi are sampled during every 500 s multiframe, setting the tc odi or tc rdi alarm. address bit symbol description
qe1m txc-04252 - 135 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 052 port 1 082 port 2 0b2 port 3 0e2 port 4 (cont.) 0 tnffb transmit port n febe error mask (force febe error): a 1 causes bit 3 (the febe value) of the v5 byte to be transmitted as a 1. this control bit is self-clearing, and will reset to 0 after the v5 byte has been transmitted. please note that if a febe is being sent as a result of a receive bip-2 error, the febe error set by this bit is transmitted afterwards. 053 port 1 083 port 2 0b3 port 3 0e3 port 4 7-3 unused unused: these bits must be written to 0. 2-0 anupsl a drop bus port n microprocessor-written signal label: the three bit positions correspond to the three signal label bits found in bits 5 through 7 in the v5 byte for the tu/vt selected. bit 2 in this register corresponds to bit 7 in the v5 byte. the bits written into this register are compared against the received signal for a mismatch signal label alarm. 054 port 1 084 port 2 0b4 port 3 0e4 port 4 7-3 unused unused: these bits must be written to 0. 2-0 bnupsl b drop bus port n microprocessor-written signal label: the three bit positions correspond to the three signal label bits found in bits 5 through 7 in the v5 byte for the tu/vt selected. bit 2 in this register corresponds to bit 7 in the v5 byte. the bits written into this register are compared against the received signal for a mismatch signal label alarm. 055 port 1 085 port 2 0b5 port 3 0e5 port 4 7-3 unused unused: these bits must be written to 0. 2-0 tn tx label transmit port n signal label: the three bit positions correspond to the three signal label bits found in bits 5 through 7 in the v5 byte for the tu/vt selected for transmission. bit 2 in this register corresponds to bit 7 in the v5 byte. 058 port 1 088 port 2 0b8 port 3 0e8 port 4 7-4 transmit k4 (z7) byte value transmit k4 (z7) value port n: the value written into bits 7, 6, 5, 4 and 0 in this register is transmitted when control bit tobwz is 0. bits 3, 2, and 1 are assigned for the rdi indicators and cannot be written to in this register. bit 7 corresponds to bit 1 in the k4 (z7) byte. 3-1 unused unused: these bits must be written to 0. 0 transmit k4 (z7) byte value transmit k4 (z7) value port n: the value written into bits 7, 6, 5, 4 and 0 in this register is transmitted when control bit tobwz is 0. bits 3, 2, and 1 are assigned for the rdi indicators and cannot be written to in this register. bit 0 corresponds to bit 8 in the k4 (z7) byte. 059 port 1 089 port 2 0b9 port 3 0e9 port 4 7-0 transmit o-bits transmit o bits port n: the value written into this register is transmitted when control bit tobwz is 0. bits 7 through 4 correspond to bits 3 through 6 in the second justification control byte. bits 3 through 0 correspond to bits 3 through 6 in the first justification control byte. 511 port 1 591 port 2 611 port 3 691 port 4 7-0 transmit v4 byte transmit v4 byte port n: the value written into this register will be trans- mitted as the v4 byte. bits 7-0 of the register correspond to bits 1-8 of the v4 byte. address bit symbol description
qe1m txc-04252 - 136 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. port n - a and b drop j2 and n2 (z6) message segments address bit symbol description 140 port 1 240 port 2 340 port 3 440 port 4 to 17f port 1 27f port 2 37f port 3 47f port 4 7-0 a side receive j2 and n2 (z6) message segments a side drop j2 and n2 (z6) message segments: the following loca- tions store the received 64-byte j2 message when control bit j2nsize is a 1, and the received 16-byte j2 message, and microprocessor-written 16-byte j2 message when j2nsize is a 0, and the received 16-byte n2 (z6) trail trace message and microprocessor-written 16-byte n2 (z6) message used for message mismatch. location message segment x40-x7f j2 message size configured for 64 bytes. the 64-byte message is written into memory with no specific start- ing address location. the n2 (z6) tandem connection feature is disabled. x40-x4f received 16-byte j2 message segment. x50-x5f microprocessor-written 16-byte j2 message segment. the starting address of the message must be written to location x50 (multiframe value of 1). x60-x6f received 16-byte n2 (z6) message segment. x70-x7f microprocessor-written 16-byte n2 (z6) message seg- ment. the starting address of the message must be written to location x70 (multiframe value of 1). 1c0 port 1 2c0 port 2 3c0 port 3 4c0 port 4 to 1ff port 1 2ff port 2 3ff port 3 4ff port 4 7-0 b side receive j2 and n2 (z6) message segments b side drop j2 and n2 (z6) message segments: the following loca- tions store the received 64-byte j2 message when control bit j2nsize is a 1, and the received 16-byte j2 message, and microprocessor-written 16-byte j2 message when j2nsize is a 0, and the received 16-byte n2 (z6) trail trace message and microprocessor-written 16-byte n2 (z6) message used for message mismatch. location message segment xc0-xff j2 message size configured for 64 bytes. the 64-byte message is written into memory with no specific start- ing address location. the n2 (z6) tandem connection feature is disabled. xc0-xcf received 16-byte j2 message segment. xd0-xdf microprocessor-written 16-byte j2 message segment. the starting address of the message must be written to location xd0 (multiframe value of 1). xe0-xef received 16-byte n2 (z6) message segment. xf0-xff microprocessor-written 16-byte n2 (z6) message seg- ment. the starting address of the message must be written to location xf0 (multiframe value of 1).
qe1m txc-04252 - 137 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 540 port 1 5c0 port 2 640 port 3 6c0 port 4 to 57f port 1 5ff port 2 67f port 3 6ff port 4 7-0 transmit j2 and n2 (z6) message segments transmit j2 and n2 (z6) message segments: the following locations store the transmitted 64-byte j2 message when control bit j2nsize is a 1, and the transmitted 16-byte j2 and n2 (z6) messages when j2nsize is a 0. location message segment 540-57f (port 1) j2 message size configured for 64 bytes. 5c0-5ff (port 2) the 64-byte message is transmitted from no 640-67f (port 3) specific starting address. the tandem 6c0-6ff (port 4) connection feature is disabled. 540-54f (port 1) j2 message size configured for 16 bytes. 5c0-5cf (port 2) the 16-byte message is transmitted with no 640-64f (port 3) specific starting address. 6c0-6cf (port 4) 560-56f (port 1) n2 (z6) message size configured for 16 bytes. 5e0-5ef (port 2) the 16-byte message is transmitted with no 660-66f (port 3) specific starting address. 6e0-6ef (port 4) address bit symbol description
qe1m txc-04252 - 138 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. package information the qe1m device is packaged in two formats. one is a 160-lead plastic quad flat package (pqfp) suitable for surface mounting, as illustrated in figure 28. figure 28. qe1m txc-04252 160-lead plastic quad flat package 120 81 80 41 40 1 160 121 lead #1 index 25.35 (sq) 28.00 (sq) 31.20 (sq) 0.65(typ) 0.20(min) 0.40(max) 4.07 (max) 0.25 (min) 3.67 see detail ? a ? 0.15 0.88 0 -10 degrees detail ? a ? see details ? b ? and ? c ? detail ? b ? detail ? c ? (typ) txc-04252aipq transwitch notes: 1. all linear dimensions are in millimeters. 2. all dimensions are nominal unless otherwise indicated.
qe1m txc-04252 - 139 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. the other is a 208-lead plastic ball grid array package (pbga) suitable for surface mounting, as illustrated in figure 29. figure 29. qe1m txc-04252 208-lead plastic ball grid array package 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 trpnmlkjhgfedcb b e e2 e d2 d note 2 d1/4 e1/4 -d1- -e1- a2 a3 a a1 dimension (note 1) min max notes: 1. all dimensions are in millimeters. values shown are for reference only. 2. identification of the solder ball a1 corner is contained within this shaded zone. this package corner may be a 90 angle, or chamfered for a1 identification. 3. size of array: 16 x 16, jedec code mo-151-aaf-1 a a1 a2 1.35 0.30 0.75 1.75 0.50 0.85 a3 (ref.) 0.36 b 0.40 0.60 d 17.00 d1 (bsc) 15.00 d2 15.00 15.70 e 17.00 e1 (bsc) 15.00 e2 15.00 15.70 e (bsc) 1.00 bottom view transwitch txc-04252aiog 16 a
qe1m txc-04252 - 140 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. ordering information part number: txc-04252aipq 160-lead plastic quad flat package (pqfp) txc-04252aiog 208-lead plastic ball grid array package (pbga) related products txc-02302b, syn155c vlsi device (155-mbit/s synchronizer, clock and data output). provides complete sts-3/stm-1 frame synchronization on incoming 155 mbit/s signals in a single low power cmos unit. it has both clock and data outputs on the line side. txc-03001b, sot-1 vlsi device (sonet sts-1 overhead terminator). in a single device, it pro- vides the sonet interface to any payload. provides access to all of the transport and path over- head defined for an sts-1/sts-n sonet signal. txc-03003b, sot-3 vlsi device (stm-1/sts-3/sts-3c overhead terminator). this device per- forms section, line, and path overhead processing for a sts-3/sts-3c/stm-1 signal. compliant with ansi and itu-tss standards. txc-03011, sot-1e vlsi device (sonet sts-1 overhead terminator). in a single device, it pro- vides the sonet interface to any payload. it provides access to all of the transport and path over- head defined for an sts-1/sts-n sonet signal. this device has extended features relative to the txc-03001b that use more input/output pins. it has a larger package. txc-04002b, adma-e1 device (2 mbit/s to tu-12 async mapper-desync). interconnects two e1 signals with any two asynchronous mode tu-12 tributaries carried in an sdh vc-4 formatted bus at the stm-1 byte rate. this is a functionally enhanced version of the txc-04002 device, and it is also a two-channel predecessor of the qe1m four-channel device. txc-04216, e1mx16 vlsi device (sixteen channel e1 to au-4/vt2 or tu-12 async map- per-desync) - e1mx16 is a module containing four qe1m chips. it interconnects sixteen e1 signals with any sixteen asynchronous mode vt2 or tu-12 tributaries carried in sdh au-4/au-3 rate pay- load interface. txc-06101, phast-1 vlsi device (sonet sts-1 overhead terminator). this device provides features similar to those of the txc-03011 sot-1e device, but it operates from a power supply of 3.3 volts rather than 5 volts. txc-06103, phast-3n vlsi device (sonet stm-1, sts-3 or sts-3c overhead terminator). this phast-3n vlsi device provides a telecom bus interface for downstream devices. it operates from a power supply of 3.3 volts.
qe1m txc-04252 - 141 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. standards documentation sources telecommunication technical standards and reference documentation may be obtained from the following organizations: ansi (u.s.a.): american national standards institute tel: (212) 642-4900 11 west 42nd street fax: (212) 302-1286 new york, new york 10036 web: www.ansi.org the atm forum (u.s.a., europe, asia): 2570 west el camino real tel: (650) 949-6700 suite 304 fax: (650) 949-6705 mountain view, ca 94040 web: www.atmforum.com atm forum europe office av. de tervueren 402 tel: 2 761 66 77 1150 brussels fax: 2 761 66 79 belgium atm forum asia-pacific office hamamatsu-cho suzuki building 3f tel: 3 3438 3694 1-2-11, hamamatsu-cho, minato-ku fax: 3 3438 3698 tokyo 105-0013, japan bellcore (see telcordia) ccitt ( see itu-t) eia (u.s.a.): electronic industries association tel: (800) 854-7179 (within u.s.a.) global engineering documents tel: (314) 726-0444 (outside u.s.a.) 7730 carondelet avenue, suite 407 fax: (314) 726-6418 clayton, mo 63105-3329 web: www.global.ihs.com etsi (europe): european telecommunications standards institute tel: 4 92 94 42 22 650 route des lucioles fax: 4 92 94 43 33 06921 sophia antipolis cedex web: www.etsi.org france
qe1m txc-04252 - 142 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. go-mvip (u.s.a.): the global organization for multi-vendor integration protocol (go-mvip) tel: (800) 669-6857 (within u.s.a.) tel: (903) 769-3717 (outside u.s.a.) 3220 n street nw, suite 360 fax: (508) 650-1375 washington, dc 20007 web: www.mvip.org itu-t (international): publication services of international telecommunication union tel: 22 730 5111 telecommunication standardization sector fax: 22 733 7256 place des nations, ch 1211 web: www.itu.int geneve 20, switzerland mil-std (u.s.a.): dodssp standardization documents ordering desk tel: (215) 697-2179 building 4 / section d fax: (215) 697-1462 700 robbins avenue web: www.dodssp.daps.mil philadelphia, pa 19111-5094 pci sig (u.s.a.): pci special interest group tel: (800) 433-5177 (within u.s.a.) 2575 ne kathryn street #17 tel: (503) 693-6232 (outside u.s.a.) hillsboro, or 97124 fax: (503) 693-8344 web: www.pcisig.com telcordia (u.s.a.): telcordia technologies, inc. tel: (800) 521-core (within u.s.a.) attention - customer service tel: (908) 699-5800 (outside u.s.a.) 8 corporate place fax: (908) 336-2559 piscataway, nj 08854 web: www.telcordia.com ttc (japan): ttc standard publishing group of the telecommunications technology committee tel: 3 3432 1551 fax: 3 3432 1553 2nd floor, hamamatsu-cho suzuki building, web: www.ttc.or.jp 1 2-11, hamamatsu-cho, minato-ku, tokyo
qe1m txc-04252 - 143 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. list of data sheet changes this change list identifies those areas within this updated qe1m data sheet that have significant differences relative to the previous and now superseded qe1m data sheet. updated qe1m data sheet: edition 3, december 2000 previous qe1m data sheet: edition 2, october 1997 the page numbers indicated below of this updated data sheet include significant changes relative to the previ- ous data sheet. page number of updated data sheet summary of the change all added transwitch document proprietary markings. changed edition number and date. all changed ? pin ? to ? lead ? throughout entire document. 1 added pbga package option to last bullet item of features list. added to list of patents. 2-3 updated table of contents and list of figures. 9 modified note and title of figure 3. 10 added figure 4. 11-20 added new column ? 208-lead pbga lead no. ? and changed column heading ? lead no. ? to ? 160-lead pqfp lead no. ? in all tables. 12 changed ? i/o ? to ? input/output ? in table footnote. 16 changed last sentence of name/function column for symbol mux. 20 added second sentence to name/function column for symbol trs . 21 modified first and second tables. moved first row from last table to first table and added note 3. modified note 2. 26-30 modified table in figure 6. added dpar and apar to figures 7 and 8. added apar to figures 9 and 10. 35-40 added address and data signal labels to tables in figures 13, 14, 15 and 16. 38-41 modified waveforms, tables and notes 3 and 4 in figures 15 and 16. 42 modified waveform and table in figure 17. 47-48 added ? unequipped operation ? section. 50 changed ? x ? to ? 0 ? in first and second rows for dv1ref column. 51 changed ? sler ? to ? sler 5 ? in first column of table and added note 5. 61 added new paragraph under ? remote defect indications ? heading. modified second heading title and title of table. switched the position of the words con- nectivity and payload in the third line of the second paragraph. 62-67 made changes in text.
qe1m txc-04252 - 144 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. 78 changed first column of second table. 80 modified last sentence in second paragraph. 84 added ? boundary scan reset ? section. 86-92 added column for pbga and its lead no. changed related comments to include pbga lead numbers. 104 added ? 1bnrdi ? for bit 4 column in first row of first table. 107 modified description column for symbol abd. 110 modified description column for bits 6 and 4 of address 013. 121 modified description column for address 0f5, bit 7. 131 added the new row for symbol 1bnrdi and changed ? 7-4 ? to ? 7-5 ? for bit col- umn in first row of table. 133 modified description column for symbol tcnen. 138, 140 removed second hyphen from device part number (now txc-04252aipq). 139 added figure 29. 140 added part number for pbga under ordering information section. 141-142 updated standard documentation sources section. 143-144 updated list of data sheet changes section. 147 updated documentation update registration form. page number of updated data sheet summary of the change
qe1m txc-04252 - 145 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. - notes - transwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. no liability is assumed as a result of their use or application. transwitch assumes no liability for transwitch applications assistance, customer product design, soft- ware performance, or infringement of patents or services described herein. nor does transwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of transwitch cov- ering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
- 146 - transwitch corporation 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453
qe1m txc-04252 - 147 of 148 - txc-04252-mb ed. 3, december 2000 data sheet proprietary transwitch corporation information for use solely by its customers. documentation update registration form if you would like to receive updated documentation for selected devices as it becomes available, please provide the information requested below (print clearly or type) then tear out this page, fold and mail it to the marketing communications department at transwitch. marketing communications will ensure that the relevant product information sheets, data sheets, application notes, technical bulletins and other publications are sent to you. you may also choose to provide the same information by fax (203.926.9453) , or by e-mail (info@txc.com) , or by telephone (203.929.8810) . most of these documents will also be made immediately available for direct download as adobe pdf files from the transwitch world wide web site ( www.transwitch.com ). name: _________________________________________________________________________________ company: __________________________________________ title: ______________________________ dept./mailstop: __________________________________________________________________________ street: _________________________________________________________________________________ city/state/zip: ___________________________________________________________________________ if located outside u.s.a., please add - country: ________________ postal code: ____________________ telephone: _______________________ ext.: ____________ fax: __________________________ e-mail: _______________________________________________ please provide the following details for the managers in charge of the following departments at your company location. department title name company/division __________________ __________________ engineering __________________ __________________ marketing __________________ __________________ please describe briefly your intended application(s) and indicate whether you would like to have a transwitch applications engineer contact you to provide further assistance: ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ if you are also interested in receiving updated documentation for other transwitch device types, please list them below rather than submitting separate registration forms: __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ please fold, tape and mail this page (see other side) or fax it to marketing communications at 203.926.9453.
please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this transwitch product as it becomes available. (fold back on this line first.) (fold back on this line second, then tape closed, stamp and mail.) transwitch corporation 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 3 enterprise drive shelton, ct 06484-4694 u.s.a. transwitch corporation attention: marketing communications dept. 3 enterprise drive shelton, ct 06484-4694 u.s.a. first class postage required

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